SPRZ578 December   2024 AM2754-Q1

 

  1.   1
  2.   Abstract
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  4. 2Silicon Revision Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2284
      2.      i2351
      3.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2120
      4.      i2137
      5.      i2189
      6.      i2196
      7.      i2199
      8.      i2249
      9.      i2253
      10.      i2278
      11.      i2279
      12.      i2310
      13.      i2311
      14.      i2312
      15.      i2383
      16.      i2401
      17.      i2427
      18.      i2431
      19.      i2435
      20.      i2436
      21.      i2438
      22.      i2455
  5. 3Trademarks
  6. 4Revision History

i2311

USART Spurious DMA Interrupts

Details:

Spurious DMA interrupts may occur when DMA is used to access TX/RX FIFO with a non-power-of-2 trigger level in the TLR register.

Workaround(s):

Use power of 2 values for TX/RX FIFO trigger levels (1, 2, 4, 8, 16, and 32).