Details

NMI has the purpose of preventing an indeterminate latency response to a critical interrupt which may be caused by software disabling interrupts for some amount of time. As such definition of NMI is that software cannot initiate masking the interrupt at that level.. which is FIQ on the Cortex R5F.

The R5F has the NMFI option that can be configured in the SEC MMR, however all interrupts are maskable in VIM. Thus a critical interrupt can still be blocked in VIM and not guaranteed to have any sort of finite interrupt response time.

Essentially this defeats the purpose.

Other Cortex R5 implementations do support NMI by not having the ability to disabled the interrupt on one or more critical channels as part of the interrupt controller definition.

Workaround

None