SWAU133 July   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Overview
    2. 2.2 Setup
    3. 2.3 Header Information
  7. 3Software
    1. 3.1 Software Description
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
  10. 6Additional Information
    1. 6.1 Trademarks

2.3 Header Information

The M2-CC3351 Add-in Card has a Gold Finger Edge that plugs into a M.2 Key E connector on the host platform board. The M2-CC3351 Gold Finger Edge pinout adapts the SDIO Based Add-in Card Pinouts (Key E) PCI Express M.2 Specification.

The signal assignment for the pins on the M.2 connector Gold Finger Edge is described in Table 3-1 and Table 3-2. Refer to Section 2.1for view of board.

Table 2-1 Top M.2 Connector (J5A) Pinout
Pin PCIe M.2 Specification Signal M2-CC3351 Signal Type/ Direction Description for M2-CC3351 Signal
P1 3.3V GND GND Board ground
P3 USB_D+ NC N/A Not connected
P5 USB_D- NC N/A Not connected
P7 GND GND GND Board ground
P9 SDIO_CLK/SYSCLK (I)(0/1.8V) SDIO_CLK Input SDIO clock or SPI clock. Must be driven by host.
P11 SDIO_CMD (I/O)(0/1.8V) SDIO_CMD Input/Output SDIO command or SPI PICO.
P13 SDIO_DATA0 (I/O)(0/1.8V) SDIO_D0 Input/Output SDIO data D0.
P15 SDIO_DATA1 (I/O)(0/1.8V) SDIO_D1 Input/Output SDIO data D1.
P17 SDIO_DATA2 (I/O)(0/1.8V) SDIO_D2 Input/Output SDIO data D2.
P19 SDIO_DATA3 (I/O)(0/1.8V) SDIO_D3 Input/Output SDIO data D3.
P21 SDIO_WAKE# (O)(0/1.8V) IRQ_WL_Option1 Output Default pin for Active Low interrupt request signal (IRQ_WL_toHost) from CC3351 to host for Wi-Fi activity.
Refer to 0 ohm resistor R7.
P23 SDIO_RESET#/TX_BLANKING (I)(0/1.8V) nRESET_Option2 Input Alternative pin to HOST_nRESET line for CC3351. Used to enable/disable (Active Low) and driven by host.
Refer to 0 ohm resistor R9 .
P25-P31 ADD-IN CARD KEY E N/A Key E Pins reserved for Key E.
P33 GND GND GND Board ground.
P35 PERp0 NC N/A Not connected.
P37 PERn0 NC N/A Not connected.
P39 GND GND GND Board ground.
P41 PETp0 NC N/A Not connected.
P43 PETn0 NC N/A Not connected.
P45 GND GND GND Board ground.
P47 REFCLKp0 NC N/A Not connected.
P49 REFCLKn0 NC N/A Not connected.
P51 GND GND GND Board ground.
P53 CLKREQ0# (I/O)( 0/1.8V/3.3V) NC N/A Not connected.
P55 PEWAKE0# (I/O)( 0/1.8V/3.3V) NC N/A Not connected.
P57 GND GND GND Board ground.
P59 RESERVED/PERo1 NC N/A Not connected.
P61 RESERVED/PERn1 NC N/A Not connected.
P63 GND GND GND Board ground.
P65 RESERVED/PETp1 NC N/A Not connected.
P67 RESERVED/PETn1 NC N/A Not connected.
P69 GND GND GND Board ground.
P71 RESERVED/REFCLKp1 NC N/A Not connected.
P73 RESERVED/REFCLKn1 NC N/A Not connected.
P75 GND GND GND Board ground.
Table 2-2 Bottom M.2 Connector (J5B) Pinout
Pin PCIe M.2 Specification Signal M2-CC3351 Signal Type/ Direction Description for M2-CC3351 Signal
P2 3.3V 3V3 Input/VCC Power provided to the board and LDO
P4 3.3V 3V3 Input/VCC Power provided to the board and LDO
P6 LED_1# (O)(OD) NC N/A Not connected
P8 PCM_CLK/I2S_SCK (I/O)(0/1.8V) NC N/A Not connected
P10 PCM_SYNC/I2S_WS (I/O)(0/1.8V) NC N/A Not connected
P12 PCM_OUT/I2S_SD_OUT (O)(0/1.8V) NC N/A Not connected
P14 PCM_IN/I2S_SD_IN (I)(0/1.8V) NC N/A Not connected
P16 LED_2# (O)(OD) NC N/A Not connected
P18 VIO_CFG (O) NC N/A Not connected
P20 UART_WAKE# (O)(0/3.3V) IRQ_BLE_toHost Output Pin for Interrupt request from CC3351 to host for BLE activity.
P22 UART_TXD (O)(0/1.8V) UART_TX Output The CC3351 UART TX to host for BLE host controller interface
P24-P30 ADD-IN CARD KEY E N/A Key E Pins reserved for Key E
P32 UART_RXD (I)(0/1.8V) UART_RX Input The CC3351 UART RX from host for BLE host controller interface
P34 UART_RTS (O)(0/1.8V) UART_RTS Output UART RTS from CC3351 to host for BLE HCI flow control
P36 UART_CTS (I)(0/1.8V) UART_CTS Input UART CTS to CC3351 from host for BLE HCI flow control
P38 VENDOR DEFINED NC N/A Not connected
P40 VENDOR DEFINED NC N/A Not connected
P42 VENDOR DEFINED NC N/A Not connected
P44 COEX3 (I/O)(0/1.8V) NC N/A Not connected
P46 COEX_TXD (O)(0/1.8V) NC N/A Not connected
P48 COEX_RXD (I)(0/1.8V) NC N/A Not connected
P50 SUSCLK (I)( 0/1.8V/3.3V) NC N/A Not connected
P52 PERST0# (I)( 0/1.8V/3.3V) NC N/A Not connected
P54 W_DISABLE2# (I)( 0/1.8V/3.3V) NC N/A Not connected
P56 W_DISABLE1# (I)(0/1.8V/3.3V) nRESET_Option1 Input Default pin to HOST_nRESET line for CC3351. Used to enable/ disable (Active Low) and Driven by host.
Refer to 0 ohm resistor R8
P58 I2C_DATA (I/O)(0/1.8 V) NC N/A Not connected
P60 I2C_CLK (I)(0/1.8 V) NC N/A Not connected
P62 ALERT# (O)(0/1.8 V) IRQ_WL_Option2 Output Alternative pin for Interrupt request Active Low (IRQ_WL_toHost) from CC3351 to host for Wi-Fi activity.
Refer to 0 ohm resistor R10.
P64 VIO 1.8V NC N/A Not connected
P66 UIM_SWP/PERST1# NC N/A Not connected
P68 UIM_POWER_SNK/CLKREQ1# NC N/A Not connected
P70 UIM_POWER_SRC/GPIO_1/PEWAKE1# NC N/A Not connected
P72 3.3V 3V3 Input/VCC Power provided to the board and LDO
P74 3.3V 3V3 Input/VCC Power provided to the board and LDO