SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The processor core and the Nested Vectored Interrupt Controller (NVIC) together prioritize and handle all exceptions.
When handling exceptions:
Software can configure the priorities of these interrupts.
Exceptions can be specified as either Secure or Non-secure. When an exception is taken, the processor switches to the associated security state. The priority of Secure and Non-secure exceptions can be programmed independently. It is possible to deprioritize Non-secure configurable exceptions using the CPU_SCB.AIRCR.PRIS bit field to enable Secure interrupts to take priority (see Section 2.5.5).
When taking and returning from an exception, the register state is always stored using the stack pointer associated with the background security state. When taking a Non-secure exception from Secure state, all the register state is stacked and then registers are cleared to prevent Secure data being available to the Non-secure handler. The vector base address (CPU_SCB:VTOR), located in the System Control Block, is banked between Secure and Non-secure state (see Section 2.5.5). VTOR_S contains the Secure vector base address, and VTOR_NS contains the Non-secure vector base address. These registers can be programmed by software, and also initialized at reset by the system.