SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The processor contains a bus matrix that arbitrates instruction fetches and memory accesses from the processor core between the external memory system and the internal System Control Space (SCS) and debug components. Priority is given to the processor to ensure that any debug accesses are as nonintrusive as possible. The system memory map is Armv8‑M Main Extension compliant, and is common both to the debugger and processor accesses. The default memory map provides user and privileged access to all regions except for the Private Peripheral Bus (PPB). The PPB space is privileged access only.
The security level associated with an address is determined by either the internal Secure Attribution Unit (SAU) or an external Implementation Defined Attribution Unit (IDAU) in the system (see Section 2.4.7.1 for more details). Some internal peripherals have memory-mapped registers in the PPB region which are banked between Secure and Non-secure state. When the processor is in Secure state, software can access both the Secure and Non-secure versions of these registers. The Non-secure versions are accessed using an aliased address. See the Armv8-M Architecture Reference Manual and Chapter 93 for more information about the memory model.