SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The watermark registers determine which parts of SRAM and Flash are considered Secure, Non-secure callable, or Non-secure. From base address and counting up, these registers define three regions which are first Secure, then Non-secure callable, then Non-secure. These settings are then used to apply the attributes to the background memory map for the Cortex M33 through the IDAU and are used in the bus matrix to block access to Secure memory from Non-secure bus initiators (for example μDMA or I2S).
The following watermark registers are described in Section 7.8.1.