SWRS205F March 2017 – December 2024 CC3120MOD
PRODUCTION DATA
Figure 7-7 shows the timing diagram for wakeup from HIBERNATE mode.
The internal 32.768-kHz XTAL is kept enabled by default when the chip goes into HIBERNATE mode in response to nHIB being pulled low.
Table 7-3 describes the timing requirements for nHIB.
ITEM | NAME | DESCRIPTION | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
Thib_min | Minimum hibernate time | Minimum pulse width of nHIB being low(1) | 10 | ms | ||
Twake_from_hib | Hardware wakeup time plus firmware initialization time | See(2) | 50 | ms |