SWRS248D April   2020  – January 2022 AWR6443 , AWR6843

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
    1.     Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions - Digital
      2. 6.2.2 Signal Descriptions - Analog
    3. 6.3 Pin Attributes
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
    6. 7.6  Power Consumption Summary
    7. 7.7  RF Specification
    8. 7.8  CPU Specifications
    9. 7.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1  Power Supply Sequencing and Reset Timing
      2. 7.10.2  Input Clocks and Oscillators
        1. 7.10.2.1 Clock Specifications
      3. 7.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.10.3.1 Peripheral Description
        2. 7.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 7.10.3.2.1 SPI Timing Conditions
          2. 7.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 7.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 7.10.3.3 SPI Peripheral Mode I/O Timings
          1. 7.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 7.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 7.10.4  LVDS Interface Configuration
        1. 7.10.4.1 LVDS Interface Timings
      5. 7.10.5  General-Purpose Input/Output
        1. 7.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 7.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins
      7. 7.10.7  Serial Communication Interface (SCI)
        1. 7.10.7.1 SCI Timing Requirements
      8. 7.10.8  Inter-Integrated Circuit Interface (I2C)
        1. 7.10.8.1 I2C Timing Requirements
      9. 7.10.9  Quad Serial Peripheral Interface (QSPI)
        1. 7.10.9.1 QSPI Timing Conditions
        2. 7.10.9.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.10.9.3 QSPI Switching Characteristics
      10. 7.10.10 ETM Trace Interface
        1. 7.10.10.1 ETMTRACE Timing Conditions
        2. 7.10.10.2 ETM TRACE Switching Characteristics
      11. 7.10.11 Data Modification Module (DMM)
        1. 7.10.11.1 DMM Timing Requirements
      12. 7.10.12 JTAG Interface
        1. 7.10.12.1 JTAG Timing Conditions
        2. 7.10.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interface
      4. 8.3.4 Host Interface
      5. 8.3.5 Main Subsystem Cortex-R4F
      6. 8.3.6 DSP Subsystem
      7. 8.3.7 Hardware Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
  9. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  11. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Tray Information for ABL, 10.4 × 10.4 mm

1 Features

  • FMCW transceiver
    • Integrated PLL, transmitter, receiver, Baseband, and ADC
    • 60- to 64-GHz coverage with 4-GHz continuous bandwidth
    • Four receive channels
    • Three transmit channels
    • Supports 6-bit phase shifter
    • Ultra-accurate chirp engine based on fractional-N PLL
    • TX power: 12 dBm
    • RX noise figure:
      • 12 dB
    • Phase noise at 1 MHz:
      • –93 dBc/Hz
  • Built-in calibration and self-test
    • Arm®Cortex®-R4F-based radio control system
    • Built-in firmware (ROM)
    • Self-calibrating system across process and temperature
    • Embedded self-monitoring with no host processor involvement on Functional Safety-Compliant devices
  • C674x DSP for advanced signal processing (AWR6843 only)
  • Hardware accelerator for FFT, filtering, and CFAR processing
  • Memory compression
  • Arm® Cortex®-R4F microcontroller for object detection, and interface control
    • Supports autonomous mode (loading user application from QSPI flash memory)
  • Internal memory with ECC
    • AWR6843:1.75 MB, divided into MSS program RAM (512 KB), MSS data RAM (192 KB), DSP L1RAM (64KB) and L2 RAM (256 KB), and L3 radar data cube RAM (768 KB)
    • AWR6443: 1.4 MB, divided into MSS program RAM (512 KB), MSS data RAM (192 KB), and L3 radar data cube RAM (768 KB)
    • Technical reference manual includes allowed size modifications
  • Other interfaces available to user application
    • Up to 6 ADC channels (low sample rate monitoring)
    • Up to 2 SPI ports
    • Up to 2 UARTs
    • 2 CAN-FD interfaces
    • I2C
    • GPIOs
    • 2 lane LVDS interface for raw ADC data and debug instrumentation
  • Device Security (on select part variants)
    • Secure authenticated and encrypted boot support
    • Customer programmable root keys, symmetric keys (256 bit), Asymmetric keys (up to RSA-2K) with Key revocation capability
    • Crypto software accelerators - PKA , AES (up to 256 bit), SHA (up to 256 bit), TRNG/DRGB
  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D
    • Hardware integrity up to ASIL-B
    • Safety-related certification
      • ISO 26262 certified up to ASIL B by TUV SUD
  • Non-Functional safety variants also available
  • AEC-Q100 qualified
  • Power management
    • Built-in LDO network for enhanced PSRR
    • I/Os support dual voltage 3.3 V/1.8 V
  • Clock source
    • 40.0 MHz crystal with internal oscillator
    • Supports external oscillator at 40 MHz
    • Supports externally driven clock (square/sine) at 40 MHz
  • Easy hardware design
    • 0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm flip chip BGA package for easy assembly and low-cost PCB design
    • Small solution size
  • Operating conditions:
    • Junction temperature range of –40°C to 125°C