SWRU455M February 2017 – October 2020 CC3120 , CC3120MOD , CC3130 , CC3135 , CC3135MOD , CC3220MOD , CC3220MODA , CC3220R , CC3220S , CC3220SF , CC3230S , CC3230SF , CC3235MODAS , CC3235MODASF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF
There are four modes of operation defined in the SPI standard. For communication to be successful, the master and slave devices must be configured in the same way.
The four SPI modes are shown in Table 25-1.
Mode | Polarity | Phase | Description |
---|---|---|---|
0 | 0 | 0 | SPI_CLK is active high and sample commences on the rising edge |
1 | 0 | 1 | SPI_CLK is active high and sample commences on the falling edge |
2 | 1 | 0 | SPI_CLK is active low and sample commences on the rising edge |
3 | 1 | 1 | SPI_CLK is active low and sample commences on the falling edge |
Figure 25-2 shows the four different timing configurations.
CC31XX is working in Mode 0. This means that data is sampled on the rising edge of the clock and changed on the falling edge of the clock. The first bit of each word must be output by the master at least half a clock cycle prior to the first clock edge.
A single 1 byte transaction in mode 0 is described in Figure 25-3.
tLead should be at least half a clock cycle long, and thus its value depends on the host clock frequency.