SWRZ095A January   2020  – June 2022 CC2642R-Q1

PRODUCTION DATA  

  1.   Abstract
  2.   Trademarks
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1.     Power_03
    2.     PKA_01
    3.     PKA_02
    4.     I2C_01
    5.     I2S_01
    6.     CPU_01
    7.     CPU_02
    8.     CPU_03
    9.     CPU_Sys_01
    10.     Sys_01
    11.     Sys_03
    12.     SYSCTRL_01
    13.     SRAM_01
    14.     GPTM_01
    15.     ADC_01
    16.     ADC_02
    17.     ADC_03
    18.     ADC_04
    19.     ADC_05
  6. 4Revision History

1 Advisories Matrix

Table 1-1 lists all advisories, modules affected, and the applicable silicon revisions.

Table 1-1 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
E/F
Power Power_03 — Increased Voltage Ripple at Low Supply Voltages When DC/DC Converter is Enabled Yes
PKA PKA_01 — Public Key Accelerator (PKA) Interrupt Line is Always High When Module is Enabled and PKA is Idle Yes
PKA PKA_02 — Public Key Accelerator (PKA) RAM is Not Byte Accessible Yes
I2C I2C_01 — I2C Module Controller Status Bit is Set Late Yes
I2S I2S_01 — I2S Bus Faults are Not Reported Yes
CPU CPU_01 — Arm® Errata #838869: Store Immediate Overlapping Exception Return Operation Might Vector to Incorrect Interrupt Yes
CPU CPU_02 — Arm® Errata #752770: Interrupted Loads to SP Can Cause Erroneous Behavior Yes
CPU CPU_03 — Arm® Errata #776924 VDIV or VSQRT Instructions Might Not Complete Correctly When Very Short ISRs are Used Yes
CPU, System CPU_Sys_01 — The SysTick Calibration Value (Register Field CPU_SCS.STCR.TENMS) Used to Set Up 10-ms Periodic Ticks is Incorrect When the System CPU is Running Off Divided Down 48-MHz Clock Yes
System Sys_01 — Device Might Boot Into ROM Serial Bootloader When Waking Up From Shutdown Yes
System Sys_03 — RTC Clock Does Not Satisfy BT Specification for Sleep Clock Accuracy (SCA) When Internal RCOSC_LF is Used as Clock Source Yes
System Controller SYSCTRL_01 — Resets Occurring in a Specific 2-MHz Period During Initial Power Up are Incorrectly Reported Yes
SRAM SRAM_01 — Reserved addresses within SRAM_MMR region alias into SRAM array Yes
General-Purpose Timer GPTM_01 — An incorrect value might be written to the general-purpose (GP) timers MMRs (memory mapped registers) when simultaneously accessing the PKA (public key accelerator) engine and/or the AES (advanced encryption standard) engine from a different controller Yes
ADC ADC_01 — Periodic ADC trigger at 200 kHz rate can be ignored when XOSC_HF is turned on or off Yes
ADC ADC_02 — ADC samples can be delayed by 2 or 14 clock cycles (24 MHz) when XOSC_HF is turned on or off, resulting in sample jitter Yes
ADC ADC_03 — Software can hang when reading the ADC FIFO if a single manual ADC trigger is generated immediately after the ADC is enabled Yes
ADC ADC_04 — Misbehaving ADC FIFO status flags in the AUX_ANAIF:ADCFIFOSTAT register (OVERFLOW, FULL, ALMOST_FULL, and EMPTY) Yes
ADC ADC_05 — Writing any value to AUX_ANAIF:ADCTRIG.START will create an ADC trigger Yes