SWRZ166 November   2024 AWR2944P

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#49
    9. 5.2  MSS#52
    10. 5.3  MSS#53
    11. 5.4  MSS#54
    12. 5.5  MSS#55
    13. 5.6  MSS#56
    14. 5.7  MSS#57
    15. 5.8  MSS#61
    16. 5.9  MSS#62
    17.     MSS#66
    18. 5.10 MSS#67
    19. 5.11 ANA#12A
    20.     ANA#37A
    21.     ANA#39
    22.     ANA#43
    23.     ANA#44
    24.     ANA#45
    25.     ANA#46
    26.     ANA#47
  7.   Trademarks
  8.   Revision History

4 Advisory to Silicon Variant / Revision Map

Table 4-1 Advisory to Silicon Variant / Revision Map
ADVISORY NUMBERADVISORY TITLEAWR2944PAWR2E44P
MAIN SUBSYSTEM
MSS#25Debugger May Display Unpredictable Data in the Memory Browser Window if a System Reset OccursXX
MSS#27MibSPI in Peripheral Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1XX
MSS#28A Data Length Error is Generated Repeatedly in Peripheral Mode When IO Loopback is EnabledXX
MSS#29Spurious RX DMA REQ From a Peripheral Mode MibSPIXX
MSS#30MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After ReadingXX
MSS#33MibSPI RAM ECC is Not Read Correctly in DIAG ModeXX
MSS#40Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoCXX

MSS#49

Issues seen in potential interoperability with receiver supporting only Strict Alignment User Flow Control Stripping during Overflow message transmission in Aurora 64B/66B ProtocolXX

MSS#52

DSS L2 Parity Issue: When DSP sends out an access beyond configured memory sizeXX

MSS#53

Incorrect behavior seen when context switch happens in the last parameter-set in HWA 2.0XX

MSS#54

Aurora TX UDP size<=4 is invalidXX

MSS#55

PMIC CLKOUT dithering in chirp-to-chirp staircase mode not supportedXX

MSS#56

CR4 STC Boot Monitor Failure XX

MSS#57

Loss of data observed on Flush/Marker or completion of packet over MDO interface. XX

MSS#61

Data aborts seen while access made to last 24 bytes of the configured MPU region and cache is enabledXX

MSS#62

HWA hangs when using back to back FFT3X paramsets

X

X

MSS#66

Potential system hang when Cortex R5 AXI Initiator Port across subsystem boundaries.XX

MSS#67

Hangup during multiple read access to MCRCXX
ANALOG / MILLIMETER WAVE
ANA#12ASecond Harmonic (HD2) Present in the Receiver XX
ANA#37AHigh RX gain droop across LO frequencyXX
ANA#39HPF cutoff frequency 2800kHz configuration can result in incorrect RX IFA gains and filter corner frequenciesXX
ANA#43Errors seen in Synthesizer Frequency Live monitorXX
ANA#44In 3.3V IO mode, back power is observed on the 1.8V rail from 3.3V rail XX
ANA#45Spurs Caused due to Digital Activity XX
ANA#46Spurs caused due to data transfer activityXX
ANA#47RX Spurs observed across RXs in Idle Channel ScenarioXX