TIDUE53I march   2018  – july 2023 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5320
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC1305M05
      5. 2.2.5  OPA4340
      6. 2.2.6  LM76003
      7. 2.2.7  PTH08080W
      8. 2.2.8  TLV1117
      9. 2.2.9  OPA350
      10. 2.2.10 UCC14240
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
        6. 2.3.1.6 Thermal Considerations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Power Supplies
        1. 2.3.4.1 Main Input Power Conditioning
        2. 2.3.4.2 Isolated Bias Supplies
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design (TMS320F28379D)
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
        4. 3.1.1.4 Microcontroller Resources Used on the Design (TMS320F280039C)
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading and Debugging the Firmware
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode - 230 VRMS, 400 V L-L
          1. 3.2.5.1.1 PFC Start-up – 230 VRMS, 400 L-L AC Voltage
          2. 3.2.5.1.2 Steady State Results at 230 VRMS, 400 V L-L - PFC Mode
          3. 3.2.5.1.3 Efficiency and THD Results at 220 VRMS, 50 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 PFC Mode - 120 VRMS, 208 V L-L
          1. 3.2.5.2.1 Steady State Results at 120 VRMS, 208 V-L-L - PFC Mode
          2. 3.2.5.2.2 Efficiency and THD Results at 120 VRMS - PFC Mode
        3. 3.2.5.3 Inverter Mode
          1. 3.2.5.3.1 Inverter Closed Loop Results
          2. 3.2.5.3.2 Efficiency and THD Results - Inverter Mode
          3. 3.2.5.3.3 Inverter - Transient Test
      6. 3.2.6 Open Loop Inverter Test Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Trademarks
  12. 6About the Authors
  13. 7Revision History

3.1.2.4 ADC Loading

To maintain synchronous operation all conversions are triggered as following:

TINV_Q1_Q3_A_PWM_BASE; that is, EPWM1 TBCTR_D_CMPB → EPWM1_SOCA (green), triggered every cycle,

TINV_Q1_Q3_A_PWM_BASE; that is, EPWM1 TBCTR_D_CMPB → EPWM1_SOCB (), triggered every 10th cycle,

TINV_Q2_Q4_A_PWM_BASE; that is, EPWM2 TBCTR_U_CMPB → EPWM2_SOCA, triggered every cycle

TINV_Q2_Q4_A_PWM_BASE; that is, EPWM2 TBCTR_D_CMPB → EPWM2_SOCB, triggered every cycle

TINV_Q1_Q3_A_PWM_BASE; that is, EPWM3 TBCTR_PERIOD → EPWM3_SOCA, triggered every cycle

Table 3-6 shows the mapping with F2837xD on the TIDA-01606 hardware.

Table 3-6 ADC Loading Architecture F28379D
ADC-A ADC-B ADC-C ADC-D

SOC0

IINV-A → ADCIN-14, CMPSS4

TEMP_A → ADC-B0

IINV-B → ADC-C4, CMPSS5

IINV-C → ADC-D2, CMPSS8

SOC1

VGRID-A → ADC-A2,

TEMP_B → ADC-B1

VGRID-B → ADC-C2

VGRID-C → ADC-D0

SOC2

VINV-A → ADC-A4

TEMP_A → ADC-B2

VINV-B → ADC-C3

VINV-C → ADC-D1

SOC3

VGRID-A → ADC-A2,

TEMP_AMB → ADC-B3

VGRID-B → ADC-C2

VBUS → ADC-D5

SOC4

VGRID-A → ADC-A2,

VGRID-B → ADC-C2

VGRID-C → ADC-D0

SOC5

VGRID-A → ADC-A2,

VGRID-B → ADC-C2

VBUS → ADC-D5

SOC6

VGRID-C → ADC-D0

SOC7

VBUS → ADC-D5

SOC8

VGRID-C → ADC-D0

SOC9

VBUS → ADC-D5

Table 3-6 shows the mapping with F280039C on the TIDA-01606 hardware.

Table 3-7 ADC Loading Architecture F280039C
ADC-A ADC-B ADC-C
SOC0 IINV-B→ ADCIN-A12, CMPSS2 IINV-C → ADCIN-B14, CMPSS3 IINV-A →ADCIN-C0, CMPSS1
SOC1 VGRID-A → ADC-A2, V_REF → ADC-B8 VGRID-C → ADC-C1
SOC2 VINV-A → ADC-A5 VGRID-B→ ADC-B0 VINV-B → ADC-C3
SOC3 VINV-C → ADC-A8 VGRID-B → ADC-B0 VBUS → ADC-C14
SOC4 VMID → ADC-A3 VGRID-B → ADC-B0 VGRID-C → ADC-C1
SOC5 VGRID-A → ADC-A2, VGRID-B → ADC-B0 VBUS → ADC-C14
SOC6 VMID → ADC-A3, TEMP_A → ADC-B3 VGRID-C → ADC-C1
SOC7 VGRID-A → ADC-A2 TEMP_B→ ADC-B2 VBUS → ADC-C14
SOC8 VMID → ADC-A3, TEMP_C → ADC-B12 VGRID-C → ADC-C1
SOC9 VGRID-A → ADC-A2 TEMP_AMB → ADC-B4 VBUS → ADC-C14
SOC10 VMID → ADC-A3
Note:

The ADC current reading is not used for the closed loop operation due to layout noise, instead SDFM bases sensing is employed to close the loop. Hence the grid current is used to close the current loop and the diagrams shall be interpreted accordingly for this change.