TIDUE53I march   2018  – july 2023 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5320
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC1305M05
      5. 2.2.5  OPA4340
      6. 2.2.6  LM76003
      7. 2.2.7  PTH08080W
      8. 2.2.8  TLV1117
      9. 2.2.9  OPA350
      10. 2.2.10 UCC14240
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
        6. 2.3.1.6 Thermal Considerations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Power Supplies
        1. 2.3.4.1 Main Input Power Conditioning
        2. 2.3.4.2 Isolated Bias Supplies
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design (TMS320F28379D)
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
        4. 3.1.1.4 Microcontroller Resources Used on the Design (TMS320F280039C)
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading and Debugging the Firmware
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode - 230 VRMS, 400 V L-L
          1. 3.2.5.1.1 PFC Start-up – 230 VRMS, 400 L-L AC Voltage
          2. 3.2.5.1.2 Steady State Results at 230 VRMS, 400 V L-L - PFC Mode
          3. 3.2.5.1.3 Efficiency and THD Results at 220 VRMS, 50 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 PFC Mode - 120 VRMS, 208 V L-L
          1. 3.2.5.2.1 Steady State Results at 120 VRMS, 208 V-L-L - PFC Mode
          2. 3.2.5.2.2 Efficiency and THD Results at 120 VRMS - PFC Mode
        3. 3.2.5.3 Inverter Mode
          1. 3.2.5.3.1 Inverter Closed Loop Results
          2. 3.2.5.3.2 Efficiency and THD Results - Inverter Mode
          3. 3.2.5.3.3 Inverter - Transient Test
      6. 3.2.6 Open Loop Inverter Test Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Trademarks
  12. 6About the Authors
  13. 7Revision History

2.3.6.2 PFC DC Bus Voltage Regulation Loop Design

Before looking at the voltage loop model, the power measurement from DQ domain can be written as:

Equation 49. GUID-20210223-CA0I-BGSW-2ZVZ-BVJGHDDTMJ0B-low.gif

where GUID-20210223-CA0I-RRJR-R25D-QCFKPTGHVZZD-low.gif

Hence:

Equation 50. GUID-20210223-CA0I-FZR0-SFR7-SKXWRQQZQB1K-low.gif
Equation 51. GUID-20210223-CA0I-NPSD-DCV1-PDWJQBWNLFQM-low.gif

The DC Bus regulation loop is assumed to be providing the power reference, which is divided by the square of the line voltages RMS to provide the conductance. When further multiplied by the line voltage gives the instantaneous current.

GUID-20210222-CA0I-6RXT-XP2T-PHJ4P8LLSKTN-low.gif Figure 2-50 Voltage Loop Model

A small-signal model of the DC bus regulation loop is developed by linearizing Equation 52 around the operating point:

Equation 52. GUID-20210223-CA0I-11DG-TR7M-TXNGDMV272SP-low.gif

Because transformation is an amplitude invariant, translating from RMS to peak quantities using GUID-20210223-CA0I-FDP1-WD1T-S7GW8KSZFNQX-low.gif and GUID-20210223-CA0I-RG49-BQHH-XH7W5NQ97BRK-low.gif, Equation 53 can be derived.

Equation 53. GUID-20210223-CA0I-BDGB-VMML-ZNLH2CHFHDPV-low.gif

Also for resistive load on the DC Bus: GUID-20210223-CA0I-M5MQ-XHZQ-XXPBWR0RS677-low.gif.

Therefore, the voltage loop plant can be written as Equation 54

Equation 54. GUID-20210326-CA0I-WVMZ-PSFT-D6LXSZ888PQN-low.gif

Using the previous model the following compensator, Equation 55 is designed for the voltage loop:

Equation 55. GUID-20210223-CA0I-1WVW-NPT1-BX9RKL6JGTJQ-low.gif

SFRA is used to measure the voltage loop bandwidth, and compare against the model which shows good correlation to the model. Figure 2-51 shows the plant frequency response comparison and Figure 2-52 shows the open-loop frequency response comparison of modelled versus measured.

GUID-20210706-CA0I-SP9G-WJ7T-RMKGKC18VBFD-low.gif Figure 2-51 Voltage Loop Plant Frequency Response Measured vs Modelled
GUID-20210223-CA0I-KWT9-PTL0-DDTJBWQZVTXT-low.png Figure 2-52 Voltage Loop, Open-Loop Frequency Response Modelled vs Measured