TIDUE73A April   2018  – November 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000 Real-Time MCU LaunchPad
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 BiSS-C Protocol
        1. 2.3.1.1 Line Delay Compensation
        2. 2.3.1.2 Processing Time Request by Encoder
        3. 2.3.1.3 Control Communication
      2. 2.3.2 C2000 BiSS-C Encoder Interface Overview
      3. 2.3.3 TIDM-1010 Board Implementation
      4. 2.3.4 MCU Resource Requirements
        1. 2.3.4.1 Input, Output Signals, and CLB Tiles
      5. 2.3.5 CLB BiSS-C Implementation Details
        1. 2.3.5.1 Transaction Waveforms
        2. 2.3.5.2 FRAME_STATE Generation
        3. 2.3.5.3 CLB_SPI_CLOCK Generation
        4. 2.3.5.4 ENCODER_CLOCK (MA) Generation
      6. 2.3.6 PM BiSS-C Interface Library
        1. 2.3.6.1 PM BiSS-C Library Functions
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1010 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Example Code
      4. 3.3.4 Encoder Test
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Software Files
  12. 6Related Documentation
    1.     Trademarks
  13. 7Terminology
  14. 8About the Authors
  15. 9Revision History

2.3.1.3 Control Communication

In BiSS-C communication, the controller can send a control frame over the MA line without interrupting the position-data communication. This is accomplished by sending one bit of the control frame within each BiSS frame.

As described in Section 2.3.1, the controller sends one data bit, known as CDM, per BiSS frame. Likewise, the encoder responds to these CDM bits with one-bit of the response, known as CDS, per BiSS frame. This is repeated until a complete control frame is sent, and response received, over several BiSS frames.

The BiSS-C control frame has two types:

  • Register communication frame: a read or write of an internal register within the encoder
  • A command frame: sends a command to the encoder
Note: As provided, TIDM-1010 does not implement the command frame. This feature can be added to the design if required by the system developer. In the command frame, the control select bit (CTS) is zero (CTS = 0). Using the command frame to support a multipoint connection is beyond the scope of this design. Therefore, this document focuses on the register communication frame only.

The following steps describe a read or write access. Refer to Figure 2-5 and Figure 2-6.

  1. The controller sends at least 14 BiSS-C frames with CDM = 0
  2. CDM = 1 indicates the start bit, S, of a control frame.
  3. The next CDM bit is referred to as CTS (control select bit). For a register access CTS is 1.
  4. The controller then sends a 3-bit ID to identify the slave being accessed.
  5. The ID is followed by a 7 bit register address and a CRC.
  6. The next 3 bits are a read bit (R), a write bit (W) and a start bit (S). R W S are defined as follows:
    • Write access: RWS equals 011b
    • Read access: RWS equals 101b
  7. The controller either:
    • Holds the CDM bit low for a read access
    • Sends the 8-bit data + CRC to be written for a write access
  8. A stop bit (P) indicates the end of the control frame.
Note: In step 6, the protocol allows the encoder to request additional processing time for the read or write. This is done by responding with S = 0 (instead of S = 1 as shown). This is not supported by the current implementation but can be added by the developer with updates to the CD state machine C code. This extra time is not required by all encoders. Refer to the specifications for your particular encoder.
TIDM-1010 Control Frame: Register Read Figure 2-5 Control Frame: Register Read
TIDM-1010 Control Frame: Register Write Figure 2-6 Control Frame: Register Write
Note: The BiSS protocol allows for back-to-back reads, or back-to-back writes, of consecutive registers. This is enabled when the controller sends a stop bit (P = 1) immediately followed by another start bit (S = 1). This feature is not implemented in TIDM-1010. Only a single read, or single write, per control frame is supported.