TIDUF17 November 2022 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
Table 3-2 shows the CPU cycles used and the CPU loading when running the reference project on the F280039C with a 120 MHz CPU clock. These numbers are based on build level 4 and use the project's default settings regarding which functions are run from RAM (such as the main ISR) and which functions are run from Flash.
CPU=120MHz | Maximum CPU Cycles For ISR | Maximum CPU Utilization [%] | Maximum MIPS Used [MIPS] |
---|---|---|---|
CPU Utilization (15-kHz ISR) | 2079 | 25.99 | 31.185 |
Table 3-3 shows how much memory is needed to run the application on the microcontroller. This memory footprint is based on the default project settings. Adding additional features (such as MTPA or vibration compenstation) or removing features (such as switching from fast_full_lib.lib to fast_simple_lib.lib to remove motor identification) results in some change to the memory footprint. As shown, a significant part of the memory is still available for performing other tasks.
Type | Used Memory on F280039C | Available Memory on F280039C | F280039C Memory Utilization |
---|---|---|---|
FLASH | 41.7 KB | 384 KB | 10.9% |
RAM | 15.3 KB | 69 KB | 22.2% |
Table 3-4 lists the peripherals used by this reference design.
Module | Purpose |
---|---|
ADCA, ADCB, ADCC | Three-phase PWM (total of 6 PWM channels) |
EPWM1, EPWM2, EPWM3 | Motor current and voltage sensing (total of 7 ADC channels) |
CMPSS1, CMPSS2, CMPSS3 | Three-phase overcurrent fault protection |
EPWMXBAR TRIP7 | CMPSS output to the EPWM trip for overcurrent protection |
MCANA | Communication |
CPU Timer 0 | Virtual timer for motor and system control in background loop |
GPIOs | One for controlCARD LED D2, One for DISABLE_FET_SUPPLY signal |