TIDUF45 May   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS127L21
      2. 2.3.2 PGA855
      3. 2.3.3 REF70
  9. 3System Design Theory
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Description
      1. 4.1.1 Board Interface
      2. 4.1.2 Power Supplies
      3. 4.1.3 Clocking Tree
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 DC Accuracy Tests
      2. 4.4.2 Gain and Offset Temperature Drift
      3. 4.4.3 Nonlinearity
      4. 4.4.4 SNR and Noise Performance
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

4.1.1 Board Interface

Table 4-1 Board Connectors and Headers
CONNECTOR DESCRIPTION
J1 QSH connector to connect to PHI, best practice is to power the board before connection
J2 SPI signals header, use for debugging and probing, or to connect to another board (if no QSH)
J3, J4, J6 Used for PGA gain control. See Table 4-2
J15 Used to probe the gain control pins
J16 Negative input
J19 Positive input
J18 Used to short the inputs together
J17, J20 Used to short the inputs to ground
J7 Positive and negative power rail inputs for the PGA855
J10, J11, J12, J13 Used to power the board externally. See Section 4.1.2 for more details
JP4, JP5 Used to select on-board LDOs or external supplies
J5 Used to connect an external reference
J9 Test points for the Vcm signal
J8 Used to connect the Vcm signal from the ADC to external equipment
J14 External clock input
JP6, JP7 Used to select the board clock or an external clock
JP1 EEPROM enable
JP2 LDO enable

The PGA gains can be adjusted by adding and removing jumpers on the gain control pins.

Table 4-2 Gain Settings
GAIN (V/v) A0 (J3) A1 (J4) A2 (J9)
0.125 0 0 0
0.25 1 0 0
0.5 0 1 0
1 1 1 0
2 0 0 1
4 1 0 1
8 0 1 1
16 1 1 1