TIDUF82A August   2024  – November 2024 DRV8162 , INA241A , ISOM8710

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Reference Design Overview
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Hardware Design
        1. 2.2.1.1 Power Stage Gate Driver
          1. 2.2.1.1.1 Gate Driver
          2. 2.2.1.1.2 Protection Features
          3. 2.2.1.1.3 VGVDD Definition
          4. 2.2.1.1.4 Strap Functions
        2. 2.2.1.2 Power Stage FETs
          1. 2.2.1.2.1 VGS versus RDS(ON)
        3. 2.2.1.3 Phase Current and Voltage Sensing
          1. 2.2.1.3.1 Phase Current
          2. 2.2.1.3.2 Phase Current – Bias Voltage Reference
          3. 2.2.1.3.3 Voltage
        4. 2.2.1.4 Host Processor Interface
        5. 2.2.1.5 Gate Drive Shutdown Path
        6. 2.2.1.6 System Diagnostic Measurements
          1. 2.2.1.6.1 Temperature Measurement
        7. 2.2.1.7 System Power Supply
          1. 2.2.1.7.1 12V Rail
          2. 2.2.1.7.2 3.3V Rail
      2. 2.2.2 Software Design
    3. 2.3 Highlighted Products
      1. 2.3.1 DRV8162L
      2. 2.3.2 INA241A
      3. 2.3.3 LMR38010
      4. 2.3.4 TMP6131
      5. 2.3.5 ISOM8710
  9. 3Hardware, Software Test Requirements and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 PCB Overview
      2. 3.1.2 Hardware Configuration
        1. 3.1.2.1 Prerequisites
        2. 3.1.2.2 Default Resistor and Jumper Configuration
        3. 3.1.2.3 Connector
          1. 3.1.2.3.1 Host Processor Interface
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Power Management
        1. 3.3.1.1 Power Up
        2. 3.3.1.2 Power Down
      2. 3.3.2 Gate Voltage and Phase Voltage
        1. 3.3.2.1 20 VDC
        2. 3.3.2.2 48 VDC
        3. 3.3.2.3 60 VDC
      3. 3.3.3 Digital PWM and Gate Voltage
      4. 3.3.4 Phase-Current Measurements
      5. 3.3.5 System Test Results
        1. 3.3.5.1 Thermal Analysis
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Authors
  12. 6Revision History
2.2.1.2.1 VGS versus RDS(ON)

The selection of specific VGVDD and VGVDD_SL voltages can define the ON state VGS, or the actual gate voltage high level of the FETs in an application.

This value can be used to find the RDS(ON) of the FET at the given voltage. The RDS(ON) is needed in defining the overcurrent trip level of the DRV8162L.

With these considerations, the calculation of the FET chosen is shown in Table 2-1. This design implements two parallel FETs to achieve low RDS(ON) and enable high-current output. The calculation was done using Ohms law.

Table 2-1 Overcurrent Trip Level of DRV8162 With Regards to FET NTMTSC1D6N10 VDS

PARAMETER

NTMTSC1D6N102 × NTMTSC1D6N10
ID267A534A
IDM900A1800A
QG106nC212nC
Junction Temperature25°C125°C25°C125°C
RDS(ON)

@ VGS = 10V

1.42mΩ2.50mΩ0.71mΩ0.88mΩ
TRIP

LEVEL1-0: 0.15V

106A

60A

211A

120A

TRIP LEVEL1-1: 0.2V

141A

80A

282A

160A

In the case of fast switching FETs, an RC snubber network was chosen on each half bridge for a test and debug option to suppress ringing of the circuit, if needed. This step was not needed for our test cases.