All trademarks are the property of their respective owners.
For decades the 555 timer has enabled system designers to create solutions for a variety of applications, including oscillators, pulse generation, and converting analog signals to pulse width modulated (PWM) signals. Depending on the 555 timer configuration, there can be limits to how flexible the device is in meeting the system designer’s need, whether it be due to the structure of the internal blocks or the tolerances of the external components used to construct the complete circuit.
Texas Instrument’s new family of smart DACs are capable of voltage output configurable waveform generation and include configurable threshold blocks that can be used to exceed the functionality of 555 timer circuits in most cases. The following sections explore a handful of common 555 timer circuits and present the alternative smart DAC solution.
A block diagram of the 555 timer is shown in Figure 2-1. It consists of an internal resistor divider between the supply voltage (VDD) and ground (GND) with each resistor equaling a nominal value of 100 kΩ. The THRESH and TRIG pins are direct inputs to the two input comparators and the CONT pin gives the user a direct input to the inverting input of the high comparator. The trigger levels of these two comparators are set to ⅓ × VDD and ⅔ × VDD due to the internal resistor divider made up of three equal resistors. Applying a voltage to the CONT pin changes the trigger levels to ½ × VCONT and VCONT. The outputs of the two comparators are fed to a flip-flop and the output of the flip-flop is sent to the base of an NPN transistor (in the case of a bipolar 555 timer) or gate of an NMOS transistor (in the case of a CMOS 555 timer) which functions as the discharge path of the device and is also sent through an inverter to the OUT pin. Therefore, when OUT is high, the discharge path between the DISCH pin and GND is disabled and when OUT is low, the discharge path is enabled. Collections of various external components can be used with these blocks to create many functional circuits.
A block diagram of the DAC53701 smart DAC is shown in Figure 2-2. A typical smart DAC consists of a I2C or SPI digital interface, a precision internal reference, and a string DAC. The internal voltage output buffer has an exposed feedback path available that can sense the output voltage. An additional feature common to smart DACs is non-volatile memory (NVM) which can store the register settings of the smart DAC for use in the field without a microcontroller. Smart DACs have general purpose input (GPI) pin handling that can be configured to control various register settings or output states. A power down logic block is included to set the output state of the smart DAC to modes such as high impedance (Hi-Z) power down, or 10-kΩ to GND power down. One final common feature of smart DACs is a continuous waveform generation (CWG) mode that can produce triangular, sawtooth, square, or sine waveforms. These features can be applied in circuits that will be discussed in the upcoming sections.
The designer can use the 555 timer in a stable operation to create an output pulse train with variable frequency and variable duty cycle. If 50% duty cycle is required, the simpler configuration shown in Figure 3-1 can be used. If a duty cycle other than 50% is required, the configuration shown in Figure 3-3 can be used.
In the 50% duty cycle configuration, the circuit is configured with the TRIG and THRESH pins tied together, which causes the circuit to re-trigger after every timing cycle. During each cycle, the capacitor charges up to the upper comparator limit of ⅔ × VDD through the external R and C and then discharges down to the lower comparator limit of ⅓ × VDD through the same external R and C. Using Equation 1 for the capacitor voltage (VCAP) in an RC circuit, it is shown that the time to charge from ⅓ × VDD to ⅔ × VDD is equal to Equation 3:
If V = VDD, VCAP (t1) = ⅓ × VDD, and VCAP (t2) = ⅔ × VDD, Equation 2 can be rewritten as:
Because the discharge time from ⅔ × VDD to ⅓ × VDD uses the same external R and C, the discharge time is equal to Equation 3:
The equal charge and discharge times produce a 50% duty cycle waveform with the frequency defined in Equation 5:
During a charging event, the OUT pin retains a high state and during a discharge event the OUT pin holds a low state. The 50% duty cycle configuration relies on OUT having a high voltage output (VOH) and low voltage output (VOL) be driven symmetrically with respect to the supply rails for tcharge to equal tdischarge. This symmetry is a characteristic of CMOS 555 timers. A bipolar 555 timer does not have symmetrical VOH/VOL characteristics and would not yield a 50% duty cycle in this configuration.
Figure 3-2 shows the resulting waveforms for a 1.5-kHz waveform with 50% duty cycle. Note that the DISCH pin can be used as an alternate output with drive characteristics on the discharge path and an external pull-up resistor.
VS = 5 V, R = 1 kΩ, C = 470 nF |
In the variable duty cycle configuration shown in Figure 3-3 the circuit is also configured with the TRIG and THRESH pins tied together, but the resistor and capacitor configuration is changed such that the capacitor charges through both RA and RB and the capacitor discharges through only RB.
This creates the asymmetric charge and discharge timings of Equation 6 and Equation 7. During a charge event, the OUT pin holds a high state and during a discharge event the OUT pin holds a low state. The configurable charge and discharge times produce a variable duty cycle waveform with the frequency defined in Equation 8 and a duty cycle defined in Equation 9.
Figure 3-4 shows the resulting waveforms for a 1.5-kHz output with a 62.5% duty cycle.
VS = 5 V, RA = 5 kΩ, RB = 7.5 kΩ C = 47 nF |
Alternatively, the designer can use a smart DAC such as the DAC53701 to create an output pulse train with variable frequency and variable duty cycle. The CWG mode of the DAC53701 has the ability to output triangle waves, sawtooth waves with rising or falling slopes, and square waves. Configuration registers are available to customize the slew rate and the high and low voltage levels of the output. This circuit is shown in Figure 3-5.
The function generator can create a 50% duty-cycle square wave with a limited number of adjustable frequencies. The frequency is given in Equation 10:
Where: SLEW_RATE is the time per high and low pulse of the square waveform.
A 50% duty cycle output pulse train with a greater number of frequencies, or a pulse train with duty cycles other than 50% can be created by using the DAC53701 in CWG mode and applying a fixed input voltage on the feedback pin (VFB) of the DAC. The DAC53701 can create a triangle wave with a frequency given by:
Where:
SLEW_RATE is given in time per step.
MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.
CODE_STEP is the programmable number of DAC codes per step.
The margin-high voltage is the high-voltage level of the waveform, and the margin-low voltage is the low-voltage level. The pulse train frequency will be equal to the frequency of the triangle wave generated by the DAC. The duty cycle of the pulse train output correlates with the margin-high voltage, margin-low voltage and voltage applied to the feedback pin (VFB), as expressed by:
Figure 3-6 shows the resulting waveforms for a 1.5-kHz output with a 60% duty cycle. An NMOS transistor may be added to the output of the DAC53701 to sharpen the edges of the output, but note this will inverse the duty cycle as shown in the simulation.
VS = 5 V, MARGIN_HIGH_CODE = 810, MARGIN_LOW_CODE = 310, CODE_STEP = 32, SLEW_RATE = 4 µs/step, MARGIN_HIGH = 4 V, MARGIN_LOW = 1.5 V, VDAC = 1.5-kHz triangle wave, and VFB = 2.5 V |
The 555 timer relies on an external capacitor as its core timing element and these components often have large tolerances on the order of 20%, leading to large variation in the output frequency. The smart DAC presents a superior option due to the internal oscillator having an accuracy of 5%.