MSPM0 G-Series MCUs Hardware Development Guide

Abstract

The MSPM0 G-series microcontroller (MCU) portfolio offers a wide variety of 32-bit MCUs with ultra-low-power and integrated analog and digital peripherals for sensing, measurement, and control applications. This application note covers information needed for hardware development with MSPM0 G series MCUs, including detailed hardware design information for power supplies, reset circuitry, clocks, debugger connections, key analog peripherals, communication interfaces, GPIOs, and board layout guidance.

Trademarks

All trademarks are the property of their respective owners.

1 MSPM0G Hardware Design Check List

Table 1-1 describes the main contents that needs to be checked during the MSPM0G hardware design process. The following sections provide more details.

Table 1-1 MSPM0G Hardware Design Check List

Pin	Description	Requirements
VDD	Power supply positive pin	Place 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins.
VSS	Power supply negative pin
VCORE	Core voltage (typical: 1.35V)	Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin.
NRST	Reset pin	Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor.
ROSC	External reference resistor pin	Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC.
VREF+	Voltage reference power supply - external reference input	When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference.
VREF-	Voltage reference ground supply - external reference input
SWCLK	Serial wire clock from debug probe	Internal pulldown to VSS, does not need any external part.
SWDIO	Bidirectional (shared) serial wire data	Internal pullup to VDD, does not need any external part.
PA0, PA1	Open-drain I/O	Pullup resistor required for output high
PA18	Default BSL invoke Pin	Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.)
PAx (exclude PA0, PA1)	General-purpose I/O	Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor.

Note: For any unused pin with a function that is shared with general-purpose I/O, follow the "PAx" unused pin connection guidelines.

TI recommends connecting a combination of a 10-μF and a 0.1-nF low-ESR ceramic decoupling capacitor to the VDD and VSS pins Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters).

The NRST reset pin is required to connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor.

The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ resistor, populated between the ROSC pin and VSS, to stabilize the SYSOSC frequency by providing a precision reference current for the SYSOSC. This resistor is not required if the SYSOSC FCL is not enabled.

For devices support external crystals, external bypass capacitors for the crystal oscillator pins are required when using external crystals.

A 0.47-µF tank capacitor is required for the VCORE pin and need to be placed close to the device with minimum distance to the device ground.

For 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high, this is required for I2C and UART functions if the ODIO are used.

Figure 1-1 MSPM0G Typical Application Schematic

2 Power Supplies in MSPM0G Devices

Power is supplied to the device through the VDD and VSS connections. The device supports operation with a supply voltage of 1.62 V to 3.6 V and can start with a 1.62-V supply. The power management unit (PMU) generates the regulated core supplies for the device and provides supervision of the external supply. It also contains a bandgap voltage reference used by the PMU and other analog peripherals. VDD is used directly to provide the IO supply (VDDIO) and the analog supply (VDDA). VDDIO and VDDA are internally connected to VDD so that additional power supply pins are not required (see the device data sheet for details).