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  • TAS5756M Digital Input, Closed-Loop Class-D Amplifier With Processing

    • SLAS988B June   2014  – August 2015 TAS5756M

      PRODUCTION DATA.  

  • CONTENTS
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  • TAS5756M Digital Input, Closed-Loop Class-D Amplifier With Processing
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Internal Pin Configurations
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  MCLK Timing
    7. 7.7  Serial Audio Port Timing - Slave Mode
    8. 7.8  Serial Audio Port Timing - Master Mode
    9. 7.9  I2C Bus Timing - Standard
    10. 7.10 I2C Bus Timing - Fast
    11. 7.11 SPK_MUTE Timing
    12. 7.12 Power Dissipation
    13. 7.13 Typical Characteristics
      1. 7.13.1 Bridge Tied Load (BTL) Configuration Curves
      2. 7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-on-Reset (POR) Function
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port
        1. 8.3.3.1 Clock Master Mode from Audio Rate Master Clock
        2. 8.3.3.2 Clock Master from a Non-Audio Rate Master Clock
        3. 8.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        4. 8.3.3.4 Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 8.3.3.4.1 Clock Generation using the PLL
          2. 8.3.3.4.2 PLL Calculation
            1. 8.3.3.4.2.1 Examples:
        5. 8.3.3.5 Serial Audio Port - Data Formats and Bit Depths
          1. 8.3.3.5.1 Data Formats and Master/Slave Modes of Operation
        6. 8.3.3.6 Input Signal Sensing (Power-Save Mode)
        7. 8.3.3.7 Serial Data Output
      4. 8.3.4 Modulation Scheme
        1. 8.3.4.1 BD-Modulation
      5. 8.3.5 miniDSP Audio Processing Engine
        1. 8.3.5.1 HybridFlow Architecture
        2. 8.3.5.2 Volume Control
          1. 8.3.5.2.1 Digital Volume Control
            1. 8.3.5.2.1.1 Emergency Volume Ramp Down
      6. 8.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
      7. 8.3.7 Error Handling and Protection Suite
        1. 8.3.7.1 Device Overtemperature Protection
        2. 8.3.7.2 SPK_OUTxx Overcurrent Protection
        3. 8.3.7.3 DC Offset Protection
        4. 8.3.7.4 Internal VAVDD Undervoltage-Error Protection
        5. 8.3.7.5 Internal VPVDD Undervoltage-Error Protection
        6. 8.3.7.6 Internal VPVDD Overvoltage-Error Protection
        7. 8.3.7.7 External Undervoltage-Error Protection
        8. 8.3.7.8 Internal Clock Error Notification (CLKE)
      8. 8.3.8 GPIO Port and Hardware Control Pins
      9. 8.3.9 I2C Communication Port
        1. 8.3.9.1 Slave Address
        2. 8.3.9.2 Register Address Auto-Increment Mode
        3. 8.3.9.3 Packet Protocol
        4. 8.3.9.4 Write Register
        5. 8.3.9.5 Read Register
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Audio Port Operating Modes
      2. 8.4.2 Communication Port Operating Modes
      3. 8.4.3 Audio Processing Modes via HybridFlow Audio Processing
      4. 8.4.4 Speaker Amplifier Operating Modes
        1. 8.4.4.1 Stereo Mode
        2. 8.4.4.2 Mono Mode
        3. 8.4.4.3 Bi-Amp Mode
        4. 8.4.4.4 Master and Slave Mode Clocking for Digital Serial Audio Port
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection Criteria
      2. 9.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 9.1.3 Amplifier Output Filtering
      4. 9.1.4 Programming the TAS5756M
        1. 9.1.4.1 Resetting the TAS5756M registers and modules
        2. 9.1.4.2 Adaptive Mode and using CRAM buffers
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step One: Hardware Integration
          2. 9.2.1.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.1.2.3 Step Three: Software Integration
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Mono (PBTL) Systems
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Step One: Hardware Integration
          2. 9.2.2.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.2.2.3 Step Three: Software Integration
        3. 9.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
      3. 9.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
        1. 9.2.3.1 Basic 2.1 System (TAS5756M Device + Simple Digital Input Amplifier)
        2. 9.2.3.2 Advanced 2.1 System (Two TAS5756M devices)
        3. 9.2.3.3 Design Requirements
        4. 9.2.3.4 Detailed Design Procedure
          1. 9.2.3.4.1 Step One: Hardware Integration
          2. 9.2.3.4.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.3.4.3 Step Three: Software Integration
        5. 9.2.3.5 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
      4. 9.2.4 2.2 (Dual Stereo BTL) Systems
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Step One: Hardware Integration
          2. 9.2.4.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.4.2.3 Step Three: Software Integration
        3. 9.2.4.3 Application Specific Performance Plots for 2.2 (Dual Stereo BTL) Systems
      5. 9.2.5 1.1 (Dual BTL, Bi-Amped) Systems
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
          1. 9.2.5.2.1 Step One: Hardware Integration
          2. 9.2.5.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.5.2.3 Step Three: Software Integration
        3. 9.2.5.3 Application Specific Performance Plots for 1.1 (Dual BTL, Bi-Amped) Systems
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
      1. 10.1.1 DVDD Supply
      2. 10.1.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
            1. 11.1.3.2.1.1 Solder Stencil
    2. 11.2 Layout Example
      1. 11.2.1 2.0 (Stereo BTL) System
      2. 11.2.2 Mono (PBTL) System
      3. 11.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
      4. 11.2.4 2.2 (Dual Stereo BTL) Systems
      5. 11.2.5 1.1 (Bi-Amped BTL) Systems
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Development Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE
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DATA SHEET

TAS5756M Digital Input, Closed-Loop Class-D Amplifier With Processing

1 Features

  • Flexible Audio I/O Configuration
    • Supports I2S, TDM, LJ, RJ Digital Input
    • 8 kHz to 192 kHz Sample Rate Support
    • Stereo Bridge Tied Load (BTL) or Mono Parallel Bridge Tied Load (PBTL) Operation
    • BD Amplifier Modulation
    • Supports 3-Wire Digital Audio Interface (No MCLK required)
  • High-Performance Closed-Loop Architecture (PVDD = 12V, RSPK = 8 Ω, SPK_GAIN = 20 dBV)
    • Idle Channel Noise = 56 µVrms (A-Wtd)
    • THD+N = 0.006 % (at 1 W, 1 kHz)
    • SNR = 104 A-Wtd (Ref. to THD+N = 1%)
  • PurePath™ HybridFlow Processing Architecture
    • Several Configurable MiniDSP Programs (called HybridFlows)
    • Download Time <100 ms (typ)
    • Advanced Audio Processing Algorithms (2)
  • Communication Features
    • Software Mode Control via I2C Port
    • Two Address Select Pins – Up to 4 Devices
  • Robustness and Reliability Features
    • Clock Error, DC, and Short-Circuit Protection
    • Over Temperature and Overcurrent Protection

2 Applications

  • LCD, LED TV, and Multi-Purpose Monitors
  • Sound Bars, Docking Stations, PC Audio
  • Wireless Subwoofers, Bluetooth and Active Speakers

3 Description

The TAS5756M device is a high-performance, stereo closed-loop amplifier with integrated audio processor with architecture. To convert from digital to analog, the device uses a high performance DAC with Burr-Brown® mixed signal heritage. It requires only two power supplies; one DVDD for low-voltage circuitry and one PVDD for high-voltage circuitry. It is controlled by a software control port using standard I2C communication. In the family, the TAS5756M uses traditional BD modulation, ensuring low distortion characteristics. The TAS5754M uses 1SPW modulation to reduce output ripple current, the expense of slightly higher distortion.

The unique HybridFlow architecture allows the system designer to choose from several configurable DSP programs that are specifically designed for use in popular audio end equipment such as bluetooth (BT) speakers, sound bars, docking stations, and subwoofers. This architecture combines the flexibility of a fully programmable device with the fast download time and ease of use of a fixed-function ROM device.

An optimal mix of thermal performance and device cost is provided in the 90 mΩ rDS(on) of the output MOSFETs. Additionally, a thermally enhanced 48-Pin HTSSOP provides excellent operation in the elevated ambient temperatures found in modern consumer electronic devices.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TAS5756M HTSSOP (48) 12.50 mm × 6.10 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.
  2. Please refer to SLAU577 for information regarding Audio Processing options available via the HybridFlow library.
  3. Tested on TAS5756MDCAEVM.


Simplified Block Diagram

TAS5756M SimpFuncDiag_slas988.gif

Power at 10% THD+N vs PVDD(3)

TAS5756M C036_BTL8RThermalRating.png

4 Revision History

Changes from A Revision (January 2015) to B Revision

  • Added TAS880021DCA device to Device Comparison TableGo
  • Clarified OCECLRTIME specification in Electrical Characteristics tableGo
  • Clarified OTECLRTIME specification in Electrical Characteristics tableGo
  • Corrected several typographical errors in Electrical Characteristics tableGo
  • Removed reference to Frequency Response graphs in Table 1Go
  • Clarified clock generation explanation in Device Clocking sectionGo
  • Clarified description of the modulation scheme used in the Class D amplifier in Modulation Scheme sectionGo
  • Added clarity to Adjustable Amplifier Gain and Switching Frequency Selection sectionGo
  • Added example resistor values for SPK_GAIN/FREQ pin configuration to Table 15Go
  • Clarified the description of overtemperature error from latching to self-clearing in Device Overtemperature Protection sectionGo
  • Corrected description of the overcurrent protection error from latching to self-clearing in SPK_OUTxx Overcurrent Protection sectionGo
  • Added clarity to I2C Communication Port sectionGo
  • Added Programming the TAS5756M sectionGo
  • Updated Table 22Go
  • Updated Table 25Go
  • Updated Table 27Go

Changes from * Revision (June 2014) to A Revision

  • Corrected typographical error in Device Information table Go
  • Updated Functional Block DiagramGo
  • Updated Table 15Go
  • Added component specification note in Application and Implementation sectionGo

5 Device Comparison Table

DEVICE NAME MODULATION STYLE PROCESSING TYPE
TAS5754MDCA 1SPW (Ternary) 50MIPs, HybridFlow (Uses mixture of RAM and ROM components to create several process flows)
TAS5756MDCA BD Modulation 50MIPs, HybridFlow (Uses mixture of RAM and ROM components to create several process flows)
TAS880021DCA 1SPW (Ternary) 100MIPs, Fixed-Function (Uses single ROM image of process flow)

6 Pin Configuration and Functions

DCA Package
48-Pin HTSSOP With PowerPAD™
Top View
TAS5756M PO_48DCA_SLAS988.gif

Pin Functions

PIN TYPE(1) INTERNAL TERMINATION DESCRIPTION
NAME NO.
ADR0 26 DI Figure 11 Sets the LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD
ADR1 20 DI Sets the second LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD
AGND 10 G — Ground reference for analog circuitry(2)
15
AVDD 14 P Figure 2 Power supply for internal analog circuitry
BSTRPA– 1 P Figure 3 Connection point for the SPK_OUTA– bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTA–
BSTRPA+ 5 P Connection point for the SPK_OUTA+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTA
BSTRPB– 48 P Connection point for the SPK_OUTB– bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTB–
BSTRPB+ 44 P Connection point for the SPK_OUTB+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTB+
CN 34 P Figure 15 Negative pin for capacitor connection used in the line--driver charge pump
CP 32 P Figure 14 Positive pin for capacitor connection used in the line-driver charge pump
CPVDD 31 P Figure 2 Power supply for charge pump circuitry
CPVSS 35 P Figure 15 –3.3-V supply generated by charge pump for the DAC
DAC_OUTA 13 AO Figure 8 Single-ended output for Channel A of the DAC
DAC_OUTB 36 AO Single-ended output for Channel B of the DAC
DGND 29 G — Ground reference for digital circuitry. Connect this pin to the system ground.
DVDD 30 P Figure 2 Power supply for the internal digital circuitry
DVDD_REG 28 P Figure 16 Voltage regulator derived from DVDD supply for use for internal digital circuitry. This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.
GND 33 G — Ground pin for device. This pin should be connected to the system ground.
GPIO0 18 DI/O Figure 11 General purpose input/output pins (GPIOx) which can be incorporated in a HybridFlow for a given purpose. Refer to documentation of target HybridFlow to determine if any of these pins are required by the HybridFlow and, if so, how they are to be used. In most HybridFlows, presentation of a serial audio signal, called SDOUT, is done through GPIO2.
GPIO1 19
GPIO2 21
GVDD_REG 8 P Figure 5 Voltage regulator derived from PVDD supply to generate the voltage required for the gate drive of output MOSFETs. This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.
LRCK/FS 25 DI/O Figure 12 Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ, and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
MCLK 22 DI Master clock used for internal clock tree and sub-circuit and state machine clocking
PGND 3 G — Ground reference for power device circuitry. Connect this pin to the system ground.
39
46
PVDD 6 P Figure 1 Power supply for internal power circuitry
7
41
42
43
SCL 17 DI Figure 10 I2C serial control port clock
SCLK 23 DI/O Figure 12 Bit clock for the digital signal that is active on the input data line of the serial data port
SDA 16 DI/O Figure 9 I2C serial control port data
SDIN 24 D1 Figure 12 Data line to the serial data port
SPK_INA– 11 AI Figure 7 Negative pin for differential speaker amplifier input A
SPK_INA+ 12 AI Positive pin for differential speaker amplifier input A
SPK_INB– 38 AI Negative pin for differential speaker amplifier input B
SPK_INB+ 37 AI Positive pin for differential speaker amplifier input B
SPK_FAULT 40 DO Figure 17 Fault pin which is pulled low when an overcurrent, overtemperature, overvoltage, undervoltage, or DC detect event occurs
SPK_GAIN/FREQ 9 AI Figure 6 Sets the gain and switching frequency of the speaker amplifier, latched in upon start-up of the device.
SPK_OUTA– 2 AO Figure 4 Negative pin for differential speaker amplifier output A
SPK_OUTA+ 4 AO Positive pin for differential speaker amplifier output A
SPK_OUTB– 47 AO Negative pin for differential speaker amplifier output B
SPK_OUTB+ 45 AO Positive pin for differential speaker amplifier output B
SPK_MUTE 27 I Figure 13 Speaker amplifier mute which must be pulled low (connected to DGND) to mute the device and pulled high (connected to DVDD) to unmute the device.
Themal pad G — Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it through solder. For proper electrical operation, this ground pad must be connected to the system ground.
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V)
(2) This pin should be connected to the system ground.

6.1 Internal Pin Configurations

TAS5756M io_equivalents_pin06.gifFigure 1. PVDD Pins
TAS5756M io_equivalents_pin01.gifFigure 3. BSTRPxx Pins
TAS5756M io_equivalents_pin08.gifFigure 5. GVDD_REG Pin
TAS5756M io_equivalents_pin11.gifFigure 7. SPK_INxx Pins
TAS5756M io_equivalents_pin16.gifFigure 9. SDA Pin
TAS5756M io_equivalents_pin18.gifFigure 11. GPIO and ADR Pins
TAS5756M io_equivalents_pin27.gifFigure 13. SPK_MUTE Pin
TAS5756M io_equivalents_pin34.gifFigure 15. CN and CPVSS Pins
TAS5756M io_equivalents_pin40.gifFigure 17. SPK_FAULT Pin
TAS5756M io_equivalents_pin14.gifFigure 2. AVDD, DVDD and CPVDD Pins
TAS5756M io_equivalents_pin02.gifFigure 4. SPK_OUTxx Pins
TAS5756M io_equivalents_pin09.gifFigure 6. SPK_GAIN/FREQ Pin
TAS5756M io_equivalents_pin13.gifFigure 8. DAC_OUTx Pins
TAS5756M io_equivalents_pin17.gifFigure 10. SCL Pin
TAS5756M io_equivalents_pin22.gifFigure 12. SCLK, BCLK, SDIN, and LRCK/FS Pins
TAS5756M io_equivalents_pin32.gifFigure 14. CP Pin
TAS5756M io_equivalents_pin28.gifFigure 16. DVDD_REG Pin

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Low-voltage digital, analog, charge pump supply DVDD, AVDD, CPVDD –0.3 3.9 V
PVDD supply PVDD –0.3 30 V
Input voltage for SPK_GAIN/FREQ and SPK_FAULT pins VI(AmpCtrl) –0.3 VGVDD + 0.3 V
DVDD referenced digital inputs(2) VI(DigIn) –0.5 VDVDD + 0.5 V
Analog input into speaker amplifier VI(SPK_INxx) –0.3 6.3 V
Voltage at speaker output pins VI(SPK_OUTxx) –0.3 32 V
Ambient operating temperature, TA –25 85 °C
Storage temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and SPK_MUTE.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V(POWER) Power supply inputs DVDD, AVDD, CPVDD 2.9 3.63 V
PVDD 4.5 26.4
RSPK Minimum speaker load BTL Mode 3 Ω
PBTL Mode 2 Ω
VIH(DigIn) Input logic high for DVDD referenced digital inputs(2)(1) 0.9 × VDVDD VDVDD V
VIL(DigIn) Input logic low for DVDD referenced digital inputs(2)(2) VDVDD 0 0.1 × VDVDD V
LOUT Minimum inductor value in LC filter under short-circuit condition 1 4.7 µH
(1) The best practice for driving the input pins of the TAS5756M device is to power the drive circuit or pullup resistor from the same supply which provides the DVDD power supply.
(2) The best practice for driving the input pins of the TAS5756M device low is to pull them down, either actively or through pulldown resistors to the system ground.

7.4 Thermal Information

THERMAL METRIC(1)(2) TAS5756M
DCA (HTSSOP)
48 PINS 		UNIT
JEDEC
STANDARD
2-LAYER PCB		 JEDEC
STANDARD
4-LAYER PCB		 TAS5756MDCAEVM
4-LAYER PCB
RθJA Junction-to-ambient thermal resistance 41.8 27.6 19.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.4 14.4 14.4 °C/W
RθJB Junction-to-board thermal resistance 9.4 9.4 9.4 °C/W
ψJT Junction-to-top characterization parameter 0.6 0.6 2 °C/W
ψJB Junction-to-board characterization parameter 8.1 9.3 4.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1 1 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) For the PCB layout, see the Using the TAS5754/6M HybridFlow Processor user's guide, SLAU577.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL I/O
|IIH|1 Input logic high current level for DVDD referenced digital input pins(2) VIN(DigIn) = VDVDD 10 µA
|IIL|1 Input logic low current level for DVDD referenced digital input pins(2) VIN(DigIn) = 0 V –10 µA
VIH1 Input logic high threshold for DVDD referenced digital inputs(2) 70% VDVDD
VIL1 Input logic low threshold for DVDD referenced digital inputs(2) 30% VDVDD
VOH(DigOut) Output logic high voltage level(2) IOH = 4 mA 80% VDVDD
VOL(DigOut) Output logic low voltage level(2) IOH = –4 mA 22% VDVDD
VOL(SPK_FAULT) Output logic low voltage level for SPK_FAULT With 100-kΩ pullup resistor 0.8 V
I2C CONTROL PORT
CL(I2C) Allowable load capacitance for each I2C Line 400 pF
fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz
fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz
VNH Noise margin at High level for each connected device (including hysteresis) 0.2 × VDD V
MCLK AND PLL SPECIFICATIONS
DMCLK Allowable MCLK duty cycle 40% 60%
fMCLK Supported MCLK frequencies Up to 50 MHz 128 512 fS(1)
fPLL PLL input frequency Clock divider uses fractional divide
D > 0, P = 1		 6.7 20 MHz
Clock divider uses integer divide
D = 0, P = 1		 1 20
SERIAL AUDIO PORT
tDLY Required LRCK/FS to SCLK rising edge delay 5 ns
DSCLK Allowable SCLK duty cycle 40% 60%
fS Supported input sample rates 8 192 kHz
fSCLK Supported SCLK frequencies 32 64 fS(1)
fSCLK SCLK frequency Either master mode or slave mode 24.576 MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
AV(SPK_AMP) Speaker amplifier gain SPK_GAIN/FREQ voltage < 3 V,
see Adjustable Amplifier Gain and Switching Frequency Selection		 20 dBV
SPK_GAIN/FREQ voltage > 3.3 V,
see Adjustable Amplifier Gain and Switching Frequency Selection		 26 dBV
ΔAV(SPK_AMP) Typical variation of speaker amplifier gain ±1 dBV
fSPK_AMP Switching frequency of the speaker amplifier Switching frequency depends on voltage presented at SPK_GAIN/FREQ pin and the clocking arrangement, including the incoming sample rate, see Adjustable Amplifier Gain and Switching Frequency Selection 176.4 768 kHz
KSVR Power supply rejection ratio Injected Noise = 50 Hz to 60 Hz, 200 mVP-P, Gain = 26 dBV, input audio signal = digital zero 60 dB
rDS(on) Drain-to-source on resistance of the individual output MOSFETs VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C, includes PVDD/PGND pins, leadframe, bondwires and metallization layers. 90 mΩ
VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C 90 mΩ
OCETHRES SPK_OUTxx Overcurrent Error Threshold 7.5 A
OTETHRES Overtemperature Error Threshold 150 °C
OCECLRTIME Time required to clear Overcurrent Error after error condition is removed. 1.3 s
OTECLRTIME Time required to clear Overtemperature Error after error condition is removed. 1.3 s
OVETHRES(PVDD) PVDD Overvoltage Error Threshold 27 V
UVETHRES(PVDD) PVDD Undervoltage Error Threshold 4.5 V
SPEAKER AMPLIFIER (STEREO BTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dBV gain, VPVDD = 12 V 2 10 mV
Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dBV gain, VPVDD = 24 V 6 15
ICN(SPK) Idle channel noise VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, A-Weighted 56 µVRMS
VPVDD = 15 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, A-Weighted 58
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted 86
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted 88
PO(SPK) Output Power (Per Channel) VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 15 W
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 20
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, THD+N = 0.1% 28
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, THD+N = 0.1% 20
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 18
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, THD+N = 0.1% 18
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 18
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, THD+N = 0.1% 12
SNR Signal-to-noise ratio (referenced to 0 dBFS input signal) VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 104 dB
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 104
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 106
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 105
THD+NSPK Total harmonic distortion and noise VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4 Ω, PO = 1 W 0.011%
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, PO = 1 W 0.007%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, PO = 1 W 0.02%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, PO = 1 W 0.015%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, PO = 1 W 0.01%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, PO = 1 W 0.017%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, PO = 1 W 0.015%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, PO = 1 W 0.017%
X-talkSPK Cross-talk (worst case between left-to-right and right-to-left coupling) VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)		 –88 dB
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)		 –97
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)		 –88
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)		 –88
SPEAKER AMPLIFIER (MONO PBTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dBV gain, VPVDD = 12 V 0.5 8 mV
Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dBV gain, VPVDD = 24 V 1 14
ICN Idle channel noise VPVDD = 15 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, A-Weighted 58 µVRMS
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, A-Weighted 57
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted 85
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted 85
PO Output Power (Per Channel) VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted 40 W
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 56
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, THD+N = 0.1% 34
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted 40
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, THD+N = 0.1% 8
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 36
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, THD+N = 0.1% 21.3
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted 36
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 24
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, THD+N = 0.1% 13.5
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted 30
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 15
SNR Signal-to-noise ratio
(referenced to 0 dBFS input signal)		 VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 104 dB
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 104
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 107
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 105
THD+N Total harmonic distortion and noise VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4 Ω, PO = 1 W 0.013%
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, PO = 1 W 0.007%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, PO = 1 W 0.02%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 2 Ω, PO = 1 W 0.028%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, PO = 1 W 0.018%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, PO = 1 W 0.017%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 2 Ω, PO = 1 W 0.027%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4 Ω, PO = 1 W 0.016%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 2 Ω, PO = 1 W 0.03%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, PO = 1 W 0.01%
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 2 Ω, PO = 1 W 0.03%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, PO = 1 W 0.012%
(1) A unit of fS indicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the TAS5756M device.
(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and SPK_MUTE.

7.6 MCLK Timing

See Figure 18.
MIN NOM MAX UNIT
tMCLK MCLK period 20 1000 ns
tMCLKH MCLK pulse width, high 9 ns
tMCLKL MCLK pulse width, low 9 ns

7.7 Serial Audio Port Timing – Slave Mode

See Figure 19.
MIN NOM MAX UNIT
fSCLK SCLK frequency 1.024 MHz
tSCLK SCLK period 40 ns
tSCLKL SCLK pulse width, low 16 ns
tSCLKH SCLK pulse width, high 16 ns
tSL SCLK rising to LRCK/FS edge 8 ns
tLS LRCK/FS Edge to SCLK rising edge 8 ns
tSU Data setup time, before SCLK rising edge 8 ns
tDH Data hold time, after SCLK rising edge 8 ns
tDFS Data delay time from SCLK falling edge 15 ns

7.8 Serial Audio Port Timing – Master Mode

See Figure 20.
MIN NOM MAX UNIT
tSCLK SCLK period 40 ns
tSCLKL SCLK pulse width, low 16 ns
tSCLKH SCLK pulse width, high 16 ns
tLRD LRCK/FS delay time from to SCLK falling edge –10 20 ns
tSU Data setup time, before SCLK rising edge 8 ns
tDH Data hold time, after SCLK rising edge 8 ns
tDFS Data delay time from SCLK falling edge 15 ns

7.9 I2C Bus Timing – Standard

MIN MAX UNIT
fSCL SCL clock frequency 100 kHz
tBUF Bus free time between a STOP and START condition 4.7 µs
tLOW Low period of the SCL clock 4.7 µs
tHI High period of the SCL clock 4 µs
tRS-SU Setup time for (repeated) START condition 4.7 µs
tS-HD Hold time for (repeated) START condition 4 µs
tD-SU Data setup time 250 ns
tD-HD Data hold time 0 900 ns
tSCL-R Rise time of SCL signal 20 + 0.1CB 1000 ns
tSCL-R1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1CB 1000 ns
tSCL-F Fall time of SCL signal 20 + 0.1CB 1000 ns
tSDA-R Rise time of SDA signal 20 + 0.1CB 1000 ns
tSDA-F Fall time of SDA signal 20 + 0.1CB 1000 ns
tP-SU Setup time for STOP condition 4 µs

7.10 I2C Bus Timing – Fast

See Figure 21.
MIN MAX UNIT
fSCL SCL clock frequency 400 kHz
tBUF Bus free time between a STOP and START condition 1.3 µs
tLOW Low period of the SCL clock 1.3 µs
tHI High period of the SCL clock 600 ns
tRS-SU Setup time for (repeated)START condition 600 ns
tRS-HD Hold time for (repeated)START condition 600 ns
tD-SU Data setup time 100 ns
tD-HD Data hold time 0 900 ns
tSCL-R Rise time of SCL signal 20 + 0.1CB 300 ns
tSCL-R1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1CB 300 ns
tSCL-F Fall time of SCL signal 20 + 0.1CB 300 ns
tSDA-R Rise time of SDA signal 20 + 0.1CB 300 ns
tSDA-F Fall time of SDA signal 20 + 0.1CB 300 ns
tP-SU Setup time for STOP condition 600 ns
tSP Pulse width of spike suppressed 50 ns

7.11 SPK_MUTE Timing

See Figure 22.
MIN MAX UNIT
tr Rise time 20 ns
tf Fall time 20 ns
TAS5756M mlck_timing_diagram_slas988.gifFigure 18. Timing Requirements for MCLK Input
TAS5756M td_pcm_aud_slv_slas988.gifFigure 19. MCLK Timing Diagram in Slave Mode
TAS5756M td_pcm_aud_mstr_slas988.gifFigure 20. MCLK Timing Diagram in Master Mode
TAS5756M td_reg_rd_slas988.gifFigure 21. I2C Communication Port Timing Diagram
TAS5756M td_xsmt_soft_mute_slas988.gifFigure 22. SPK_MUTE Timing Diagram for Soft Mute Operation via Hardware Pin

7.12 Power Dissipation

VPVDD
(V)		 SPK_GAIN(1)(2)(3)
(dBV) 		fSPK_AMP
(kHz)		 STATE OF
OPERATION 		RSPK
(Ω)		 IPVDD(4)
(mA)
IDVDD(5)
(mA)
PDISS
(W)
7.4 20 384 Idle 4 21.3 35 0.273
6 21.33 35 0.273
8 21.3 35 0.273
Mute 4 21.33 35 0.273
6 21.34 35 0.273
8 21.36 35 0.274
Standby 4 2.08 17 0.071
6 2.11 17 0.072
8 2.17 17 0.072
Powerdown 4 2.03 1 0.018
6 2.04 1 0.018
8 2.06 1 0.019
768 Idle 4 27.48 35 0.319
6 27.49 35 0.319
8 24.46 35 0.297
Mute 4 27.5 35 0.319
6 27.51 35 0.319
8 27.52 35 0.319
Standby 4 2.04 17 0.071
6 2.08 17 0.071
8 2.11 17 0.072
Powerdown 4 2.06 1 0.019
6 2.07 1 0.019
8 2.08 1 0.019
11.1 20 384 Idle 4 24.33 35 0.386
6 24.32 35 0.385
8 24.36 35 0.386
Mute 4 24.36 35 0.386
6 24.32 35 0.385
8 24.37 35 0.386
Standby 4 3.58 17 0.096
6 3.57 17 0.096
8 3.58 17 0.096
Powerdown 4 3.52 1 0.042
6 3.52 1 0.042
8 3.54 1 0.043
768 Idle 4 30.7 35 0.456
6 30.65 35 0.456
8 30.67 35 0.456
Mute 4 3.072 35 0.150
6 30.69 35 0.456
8 30.69 35 0.456
Standby 4 3.54 17 0.095
6 3.54 17 0.095
8 3.58 17 0.096
Powerdown 4 3.53 1 0.042
6 3.53 1 0.042
8 3.55 1 0.043
12 20 384 Idle 4 25.07 35 0.416
6 25.08 35 0.416
8 25.1 35 0.417
Mute 4 25.12 35 0.417
6 25.08 35 0.416
8 25.11 35 0.417
Standby 4 3.92 17 0.103
6 3.93 17 0.103
8 3.94 17 0.103
Powerdown 4 3.87 1 0.050
6 3.85 1 0.050
8 3.87 1 0.050
768 Idle 4 31.31 35 0.491
6 31.29 35 0.491
8 31.31 35 0.491
Mute 4 31.31 35 0.491
6 31.33 35 0.491
8 31.32 35 0.491
Standby 4 3.88 17 0.103
6 3.9 17 0.103
8 3.91 17 0.103
Powerdown 4 3.89 1 0.050
6 3.91 1 0.050
8 3.88 1 0.050
15 26 384 Idle 4 27.94 35 0.535
6 27.91 35 0.534
8 27.75 35 0.532
Mute 4 27.98 35 0.535
6 27.94 35 0.535
8 27.88 35 0.534
Standby 4 5.09 17 0.132
6 5.12 17 0.133
8 5.19 17 0.134
Powerdown 4 5.02 1 0.079
6 5.06 1 0.079
8 5.14 1 0.080
768 Idle 4 33.05 35 0.611
6 33.03 35 0.611
8 33.08 35 0.612
Mute 4 33.03 35 0.611
6 33.04 35 0.611
8 33.05 35 0.611
Standby 4 5.07 17 0.132
6 5.09 17 0.132
8 5.14 17 0.133
Powerdown 4 5.02 1 0.079
6 5.04 1 0.079
8 5.09 1 0.080
19.6 26 384 Idle 4 32.27 35 0.748
6 32.19 35 0.746
8 32.08 35 0.744
Mute 4 32.27 35 0.748
6 32.24 35 0.747
8 32.22 35 0.747
Standby 4 6.95 17 0.192
6 6.93 17 0.192
8 7 17 0.193
Powerdown 4 6.89 1 0.138
6 6.9 1 0.139
8 6.96 1 0.140
768 Idle 4 34.99 35 0.801
6 34.95 35 0.801
8 34.97 35 0.801
Mute 4 34.96 35 0.801
6 34.98 35 0.801
8 34.96 35 0.801
Standby 4 6.93 17 0.192
6 6.93 17 0.192
8 6.98 17 0.193
Powerdown 4 6.84 1 0.137
6 6.89 1 0.138
8 6.9 1 0.139
24 26 384 Idle 4 36.93 35 1.002
6 36.87 35 1.000
8 36.77 35 0.998
Mute 4 36.94 35 1.002
6 36.89 35 1.001
8 36.85 35 1.000
Standby 4 8.73 17 0.266
6 8.72 17 0.265
8 8.71 17 0.265
Powerdown 4 8.64 1 0.211
6 8.66 1 0.211
8 8.69 1 0.212
768 Idle 4 36.84 35 1.000
6 36.86 35 1.000
8 36.83 35 0.999
Mute 4 36.85 35 1.000
6 36.84 35 1.000
8 36.82 35 0.999
Standby 4 8.66 17 0.264
6 8.68 17 0.264
8 8.71 17 0.265
Powerdown 4 8.63 1 0.210
6 8.64 1 0.211
8 8.65 1 0.211
(1) Mute: P0-R3-B0,B5 = 1
(2) Standby: P0-R2-B5 = 1
(3) P0-R2-B0 = 1
(4) IPVDD refers to all current that flows through the PVDD supply for the DUT. Any other current sinks not directly related to the DUT current draw were removed.
(5) IDVDD refers to all current that flows through the DVDD (3.3-V) supply for the DUT. Any other current sinks not directly related to the DUT current draw were removed.

7.13 Typical Characteristics

All performance plots were taken using the TAS5754M-56MEVM at room temperature, unless otherwise noted. The term Traditional LC filter refers to the output filter that is present by default on the EVM. For Filterless measurements, the on-board LC filter was removed and an Audio Precision AUX-025 measurement filter was used to take the measurements.

Table 1. Quick Reference Table

OUTPUT
CONFIGURATIONS		 PLOT TITLE FIGURE NUMBER
Bridge Tied Load (BTL) Configuration Curves Output Power vs PVDD Figure 23
THD+N vs Frequency, VPVDD = 12 V Figure 24
THD+N vs Frequency, VPVDD = 15 V Figure 25
THD+N vs Frequency, VPVDD = 18 V Figure 26
THD+N vs Frequency, VPVDD = 24 V Figure 27
THD+N vs Power, VPVDD = 12 V Figure 28
THD+N vs Power, VPVDD = 15 V Figure 29
THD+N vs Power, VPVDD = 18 V Figure 30
THD+N vs Power, VPVDD = 24 V Figure 31
Idle Channel Noise vs PVDD Figure 32
Efficiency vs Output Power Figure 33
Idle Current Draw (Filterless) vs PVDD Figure 34
Idle Current Draw (Traditional LC Filter) vs PVDD Figure 35
Crosstalk vs. Frequency Figure 36
PVDD PSRR vs Frequency Figure 37
DVDD PSRR vs Frequency Figure 38
AVDD PSRR vs Frequency Figure 39
CPVDD PSRR vs Frequency Figure 40
Powerdown Current Draw vs PVDD Figure 41
Parallel Bridge Tied Load (PBTL) Configuration Output Power vs PVDD Figure 42
THD+N vs Frequency, VPVDD = 12 V Figure 43
THD+N vs Frequency, VPVDD = 15 V Figure 44
THD+N vs Frequency, VPVDD = 18 V Figure 45
THD+N vs Frequency, VPVDD = 24 V Figure 46
THD+N vs Power, VPVDD = 12 V Figure 47
THD+N vs Power, VPVDD = 15 V Figure 48
THD+N vs Power, VPVDD = 18 V Figure 49
THD+N vs Power, VPVDD = 24 V Figure 50
Idle Channel Noise vs PVDD Figure 51
Efficiency vs Output Power Figure 52
Idle Current Draw (filterless) vs PVDD Figure 57
Idle Current Draw (traditional LC filter) vs PVDD Figure 58
PVDD PSRR vs Frequency Figure 53
DVDD PSRR vs Frequency Figure 54
AVDD PSRR vs Frequency Figure 55
CPVDD PSRR vs Frequency Figure 56
Powerdown Current Draw vs PVDD Figure 59

7.13.1 Bridge Tied Load (BTL) Configuration Curves

Return to Quick Reference Table.

TAS5756M C036_BTL8RThermalRating.png
AV(SPK_AMP) = 26 dBV
Figure 23. Output Power vs PVDD – BTL
TAS5756M C002_BTLTHDvFreq15V4R6R8R.png
AV(SPK_AMP) = 20 dBV PO = 1 W VPVDD = 15 V
Figure 25. THD+N vs Frequency – BTL
TAS5756M C003_BTLTHDvFreq24V4R6R8R.png
AV(SPK_AMP)
= 26 dBV 		PO = 1 W VPVDD = 24 V
Figure 27. THD+N vs Frequency – BTL
TAS5756M C004_BTLTHDvPo15V4R6R8R.png
AV(SPK_AMP)
= 20 dBV 		Input Signal = 1 kHz Sine VPVDD = 15 V
Figure 29. THD + N vs Power – BTL
TAS5756M C005_BTLTHDvPo24V4R6R8R.png
AV(SPK_AMP) = 26 dBV PO = 1 W VPVDD = 24 V
Figure 31. THD + N vs Power – BTL
TAS5756M C007_BTLEffvPo12V15V18V24V8R.png
RSPK = 8 Ω
Figure 33. Efficiency vs Output Power – BTL
TAS5756M C015_BTLIdleLCv4p5to24V8R.png
fSPK_AMP = 768 kHz RSPK = 8 Ω
Figure 35. Idle Current Draw
(Traditional LC Filter) vs PVDD – BTL
TAS5756M C009_BTLPVDDPSRRvFreq24V4R6R8.png
AV(SPK_AMP) = 26 dBV Supply Noise = 250 mV
VPVDD = 24 V Sine Input
Figure 37. PVDD PSRR vs Frequency – BTL
TAS5756M C011_BTLAVDDPSRRvFreq24V8R.png
AV(SPK_AMP) = 26 dBV Supply Noise = 250 mV
VPVDD = 24 V RSPK = 8 Ω
Figure 39. AVDD PSRR vs Frequency – BTL
TAS5756M C014_BTLShtdwnv4p5to24V8R.png
AV(SPK_AMP) = 26 dBV fSPK_AMP = 786 kHz
Figure 41. Powerdown Current Draw vs PVDD – BTL
TAS5756M C034_BTLTHDvFreq12V4R6R8R.png
AV(SPK_AMP) = 20 dBV PO = 1 W VPVDD = 12 V
Figure 24. THD+N vs Frequency – BTL
TAS5756M C038_BTLTHDvFreq18V4R6R8R.png
AV(SPK_AMP) = 20 dBV PO = 1 W VPVDD = 18 V
Figure 26. THD+N vs Frequency – BTL
TAS5756M C035_BTLTHDvPo12V4R6R8R.png
AV(SPK_AMP)
= 20 dBV 		Input Signal = 1 kHz Sine VPVDD = 12 V
Figure 28. THD + N vs Power – BTL
TAS5756M C039_BTLTHDvPo18V4R6R8R.png
AV(SPK_AMP)
= 26 dBV 		Input Signal = 1 kHz Sine VPVDD = 18 V
Figure 30. THD + N vs Power – BTL
TAS5756M C006_BTLICNvPVDD4p5to24V8R.png
AV(SPK_AMP) = 20 dBV fSPK_AMP = 384 kHz RSPK = 8 Ω
Figure 32. Idle Channel Noise vs PVDD – BTL
TAS5756M C013_BTLIdleFltrlssv4p5to24V8R.png
fSPK_AMP = 768 kHz RSPK = 8 Ω
Figure 34. Idle Current Draw (Filterless) vs VPVDD – BTL
TAS5756M C008_BTLXtlkvFreq24V1W4R6R8R.png
AV(SPK_AMP) = 26 dBV Sine Input VPVDD = 24 V
Figure 36. Crosstalk vs Frequency – BTL
TAS5756M C010_BTLDVDDPSRRvFreq24V8R.png
AV(SPK_AMP) = 26 dBV Supply Noise = 250 mV
VPVDD = 24 V RSPK = 8 Ω
Figure 38. DVDD PSRR vs Frequency – BTL
TAS5756M C012_BTLCPVDDPSRRvFreq24V8R.png
AV(SPK_AMP) = 26 dBV Supply Noise = 250 mV
VPVDD = 24 V Sine Input
Figure 40. CPVDD PSRR vs Frequency – BTL

7.13.2 Parallel Bridge Tied Load (PBTL) Configuration

Return to Quick Reference Table.

TAS5756M C037_PBTLThermalRating.png
AV(SPK_AMP) = 26 dBV Measured on TAS5754/6 EVM
Figure 42. Output Power vs PVDD – PBTL
TAS5756M C018_PBTLTHDvFreq15V2R4R6R.png
AV(SPK_AMP) = 20 dBV PO = 1 W VPVDD = 15 V
Figure 44. THD+N vs Frequency – PBTL
TAS5756M C020_PBTLTHDvFreq24V2R4R6R.png
AV(SPK_AMP) = 26 dBV PO = 1 W VPVDD = 24 V
Figure 46. THD+N vs Frequency – PBTL
TAS5756M C022_PBTLTHDvPo15V2R4R6R.png
AV(SPK_AMP) = 20 dBV
 PO = 1 W VPVDD = 15 V
Figure 48. THD+N vs Power – PBTL
TAS5756M C024_PBTLTHDvPo24V2R4R6R.png
AV(SPK_AMP) = 20 dBV PO = 1 W
VPVDD = 24 V Input Signal = 1 kHz Sine
Figure 50. THD+N vs Power – PBTL
TAS5756M C026_PBTLEffvPo12V15V18V24V4R.png
AV(SPK_AMP) = 26 dBV ILOAD = xA VPVDD = 24 V
Figure 52. Efficiency vs Output Power – PBTL
TAS5756M C028_PBTLDVDDPSRRvFreq24V.png
AV(SPK_AMP) = 26 dBV RSPK = 8 Ω
VPVDD = 24 V Supply Noise = 250 mV
Figure 54. DVDD PSRR vs Frequency – PBTL
TAS5756M C030_PBTLCPVDDPSRRvFreq24V2R.png
AV(SPK_AMP) = 26 dBV Sine Input
VPVDD = 24 V Supply Noise = 250 mV
Figure 56. CPVDD PSRR vs Frequency – PBTL
TAS5756M C033_PBTLIdleLCv4p5to24V4R.png
Figure 58. Idle Current Draw
(Traditional LC filter) vs PVDD – PBTL
TAS5756M C017_PBTLTHDvFreq12V2R4R6R.png
AV(SPK_AMP) = 20 dBV PO = 1 W VPVDD = 12 V
Figure 43. THD+N vs Frequency – PBTL
TAS5756M C019_PBTLTHDvFreq18V2R4R6R.png
AV(SPK_AMP) = 26 dBV PO = 1 W VPVDD = 18 V
Figure 45. THD+N vs Frequency – PBTL
TAS5756M C021_PBTLTHDvPo12V2R4R6R.png
AV(SPK_AMP) = 20 dBV PO = 1 W VPVDD = 12 V
Figure 47. THD+N vs Power – PBTL
TAS5756M C023_PBTLTHDvPo18V2R4R6R.png
AV(SPK_AMP) = 20 dBV PO = 1 W
VPVDD = 18 V Input Signal = 1 kHz Sine
Figure 49. THD+N vs Power – PBTL
TAS5756M C025_PBTLICNvPVDD4p5to24V4R.png
AV(SPK_AMP)
= 26 dBV 		ILOAD = xA VPVDD = 18 V
Figure 51. Idle Channel Noise vs PVDD – PBTL
TAS5756M C027_PBTLPVDDPSRRvFreq24V2R4R6R.png
AV(SPK_AMP) = 26dBV Sine Input VPVDD = 24V
Figure 53. PVDD PSRR vs Frequency – PBTL
TAS5756M C029_PBTLAVDDPSRRvFreq24V2R.png
AV(SPK_AMP) = 26 dBV RSPK = 8 Ω
VPVDD = 24 V Supply Noise = 250 mV
Figure 55. AVDD PSRR vs Frequency – PBTL
TAS5756M C031_PBTLIdleFltrlssv4p5to24V4R.png
Figure 57. Idle Current Draw (Filterless) vs PVDD – PBTL
TAS5756M C032_PBTLShtdwnv4p5to24V4R.png
AV(SPK_AMP) = 26 dBV fSPK_AMP = 786 kHz
Figure 59. Powerdown Current Draw vs PVDD – PBTL

 
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