Table 2-1 compares the parameters of silicon/IGBT, SiC and GaN devices. The reason why the vast majority of designs use silicon is because silicon still has a cost advantage over wide-bandgap devices. This gap will likely become smaller in the near future.

Wide-bandgap devices come into play when the design calls for the transfer of high power in a specified form factor and silicon-based solutions reach their thermal limits, either generating too many losses or requiring too many semiconductor components in parallel to keep the losses at bay, which can lead to a more expensive overall solution.

GaN high-electron mobility transistors enable designers to reach higher power density levels than any other technology on the market. Their parasitic elements are smaller compared to silicon and SiC devices, allowing switching at higher frequencies with acceptable losses. Direct drive of TI GaN FETs results in a zero reverse-recovery charge characteristic, which is beneficial for hard-switched continuous conduction mode (CCM) topologies such as the CCM totem-pole PFC converter [5]. CCM totem-pole PFC converters with silicon switches have never been viable given the immense losses caused by the large reverse-recovery charge of silicon metal-oxide semiconductor field-effect transistors (MOSFETs).

Writing this paper called for a performance comparison between SiC MOSFETs and GaN. To accurately compare TI GaN devices with ultra-fast slew rates (>150 V/ns), you would need to consider SiC MOSFETs in a low-inductance package with fast-switching-speed capability. In the commercial market, however, SiC FETs with similar R_DS(on) and voltage ratings are not readily available in a low-inductance package with a Kelvin source connection. So instead, SiC FETs with a larger R_DS(on) were tested and used the switching figure-of-merit (FOM) concept for both hard- and soft-switching comparisons, as shown in Figure 2-1 and Figure 2-2.

From the FOM graphs, you can see that under soft switching, TI GaN has an immense advantage over SiC MOSFETs, with significantly lower turnoff losses as a result of the direct-drive approach. In hard-switching conditions, the total switching loss includes both turnon and turnoff energy losses. The overall switching losses are proportional to the product of the switching frequency and energy required to turn the respective FET on and off. Equation 1 expresses this relationship:

The hard-switching FOM shows that TI GaN generates fewer losses at load currents greater than 15 A and is a better fit for high-current applications.

Two types of parasitic inductance between the driver and the FET limit the ultra-fast switching performance of GaN FETs: the common source inductance (CSI) and the gate-loop inductance. Minimizing both parasitic elements will help achieve the best possible switching performance.

A completely discrete approach will result in a large CSI because of inductance contributions from the integrated circuit (IC) packages and the driver to FET routing distance on the printed circuit board (PCB). The result will cause slower turnon of the GaN FET, with increased losses. Most GaN FET manufacturers currently only offer packages with a separate Kelvin source connection to reduce the CSI. A discrete FET solution with an external gate driver will have a larger CSI compared to the integrated driver and GaN solution from TI (see Figure 3-1 through Figure 3-4).

Meanwhile, integrating the driver and GaN also minimizes the gate-loop inductance, helping reduce gate-loop ringing, mitigating crosstalk, and improving gate reliability [6][7][8].

Figure 3-5 shows the simulated turnon switching waveforms of the high-side FET in a GaN FET half bridge for two different CSI values (0 nH and 5 nH).

Having the smallest possible CSI enables the GaN FET to turnon much faster, without causing any switch-node ringing. In addition, the turnon switching losses of the GaN FET are smaller with a lower CSI value, which helps improve system efficiency (see Figure 3-6).

There is a similar effect for the parasitic gate-loop inductance. Figure 3-7 illustrates that the smaller the gate-loop inductance value, the smaller the energy required to turnon the GaN FET (2 nH and 10 nH).

The GaN-Based 6.6-kW Bidirectional Onboard Charger Reference Design [2] supports operation from a universal single-phase input off the AC grid and provides full output power (6.6 kW) to the load at an input voltage of 208 VAC and above. Below this input voltage level, the output power is linearly derated. The main target of this reference design is to deliver the maximum possible power to the battery, with a power density level greater than 60 W/inch3 (3.66 kW/L) and a battery voltage range between 250 V and 450 V. Additionally, this OBC design supports bidirectional operation. Table 4-1 lists the power-supply specifications.

Figure 4-1 is a block diagram of the 6.6-kW OBC reference design.

Both the PFC stage and the DC/DC converter leverage 30-mΩ automotive-qualified 650-V LMG3522R030-Q1 GaN FETs for control by a single C2000™ TMS320F28388D real-time microcontroller (MCU). In total, the converters use 12 GaN FETs; the low-frequency FETs for the bridgeless input rectifier are regular silicon MOSFETs.

To reach a power density target of more than 60 W/inch³, it’s important to design the PFC with the smallest possible number of components while still maintaining good efficiency and keeping the components within their thermal limits. With these requirements, the topology of choice is the totem-pole bridgeless PFC [10][11].

After having selected the PFC topology, the next step in the design process is to decide on a mode of operation: CCM or critical conduction mode (CrCM). For both modes of operation, Figure 5-1 illustrates the envelope of the actual current waveform and the average current waveform for a single AC half cycle.

The average current is identical for both modes, but by leveraging different inductance values and control schemes, the shape of the actual current waveform is completely different.

CCM operation offers a smaller inductor current ripple and thus smaller root-mean-square (RMS) current stress in the FETs. CrCM operation enables zero-voltage switching of the FETs when the input voltage is smaller than half the output voltage. For higher input voltages, it is possible to turnon the FETs with a reduced voltage, because the current always returns to 0 A before every new switching cycle.

With CCM operation, the power stage is hard switching, which means that the FETs will exhibit losses at every turnon and turnoff transition. Thus, CCM produces higher switching losses in the FETs than CrCM operation.

Large reverse-recovery charge losses would prevent the use of CCM operation with silicon FETs. In CrCM, there are no reverse-recovery losses because the current always returns to 0 A. Given the zero reverse-recovery charge characteristic of directly driven TI GaN FETs, these losses are also out of the equation for CCM operation and make it an attractive alternative.

Choosing an inductance value for CrCM operation that’s several times smaller than in CCM has the potential to reduce inductor size. The peak and RMS currents in the FETs will be several times larger than in CCM, however.

For the 6.6-kW OBC reference design and its 30-mΩ TI GaN FETs, the larger RMS currents would have required the use of a three-phase CrCM PFC approach in order to keep all components within their thermal limits. In CCM, with a two-phase approach, the GaN FETs would stay within their thermal limits.

A multiphase approach distributes the losses among more components and spreads them to a wider area. In addition, these components may have slightly more disadvantageous parameters, such as higher direct current resistance (DCR) and lower I_sat for inductors, or higher R_DS(on) for the FETs than in a single-phase configuration. Thus, leveraging a multiphase converter makes it easier to find more cost-effective and fitting components for a high-power design.

Figure 5-2 shows the relative loss reduction for one-, two- and three-phase 6.6-kW CCM PFC switching at 120 kHz. The loss reduction from one to two phases is roughly 40%. Adding a third phase makes sense if the main design target is to maximize efficiency.

Three factors determine the choice of operating switching frequency: the power density target, the efficiency and the electromagnetic interference (EMI) limit lines. There will have to be a trade-off between raising the switching frequency to improve the power density and reducing the switching frequency to optimize converter efficiency.

It is also important to remember the worst-case limit lines of the EMI standard against those you need to test the design to test the design. For multiphase converters, consider the effective switching frequency for the electromagnetic measurement, which is n-times the base switching frequency of each phase, where n is the number of phases. You also need to consider that the switching frequency for a PFC converter operating in CrCM is variable, which requires a more complex EMI filter design. Figure 5-3 shows the limit lines for CISPR 32 Class B.

A switching frequency of 120 kHz was chosen for this design, as the losses per GaN device would still keep them comfortably below the recommended maximum junction temperature, while the power dissipation is in a range that enables PFC efficiency of more than 98%.

Figure 5-4 illustrates the TI GaN FET losses over switching frequency for two different thermal resistances. The end of each graph indicates where the device reaches its maximum acceptable junction temperature.

Using a negatively coupled inductor instead of two separate PFC inductors will further improve the power density of an interleaved dual-phase totem-pole PFC converter. Negative coupling means that the orientation of the coupled winding ends is inverted (as shown in Figure 4-1), where the coupling dots are located at opposite sides.

The resulting ripple-current cancellation in this negatively coupled configuration can significantly lower the required inductance for each leg compared to a single inductor, while having a similar output ripple level. And, also introduces the option to use a slightly smaller core. For this design, the volume reduction was around 30% compared to a two-phase PFC implementation using two separate inductors.

Figure 5-5 shows the effect of the coupling coefficient on the RMS current per phase for different self-inductance values.

Choosing the correct values for the self- and mutual inductance of this coupled inductor is a bit tricky, because the optimal simulated results are mechanically not manufacturable, as indicated by the grayed-out area in Figure 5-5. Only by having a “bad” coupling coefficient can you achieve the optimal ripple-current cancellation. The worse coupling also reduces the common-mode noise generated by the coupled inductor.

When using an interleaved approach, two phases with a 180-degree phase shift and negative coupling yield better ripple-current cancellation than positive coupling. The coupled inductor used in the 6.6-kW OBC reference design leverages two stacked 0079439A7 Kool Mµ® Max 60-µ cores with 77 µH of self-inductance, a coupling coefficient of 55% and a DCR of 12 mΩ per winding.

Measured efficiency data for the PFC (Figure 5-6) shows that it is possible to reach more than 98% efficiency at 30% output power and above, leveraging 650-V 30-mΩ GaN FETs in a very compact form factor.

The primary goals for the GaN-based OBC reference design are to minimize overall solution volume and maximize the electrical efficiency of the power conversion. To effectively optimize these parameters, the DC/DC stage must meet a few critical requirements. First and foremost, this converter is a battery charger. The wide range of output voltage values that the output needs to cover present significant challenges to many topologies; see the highlighted levels in Table 6-1. For example, a popular topology such as an inductor-inductor-capacitor (LLC) converter may have some difficulty meeting high efficiency over such a wide output range. In addition, the bidirectional nature of the converter might require a traditional LLC to have some additional tank components and facilitate the necessary gain.

The final solution achieved an efficiency of just over 98%, as shown in Figure 6-1.

For context, Figure 6-2 shows some essential waveforms during operation at full load.

Topology selection, operating frequency, tank design, operating modes, thermal management, layout and control optimization are among some of the more significant design challenges that we solved in the course of the GaN-based OBC reference design. Now, let us explore these challenges more, along with the rationale behind our decision-making.

In order to determine how to meet size, efficiency and output voltage regulation requirements, we evaluated two topologies in detail: the CLLLC (Figure 7-1) and the dual active bridge (DAB) (Figure 7-2).

Both of these converters have the same fundamental structure. They both have a full bridge on the primary and secondary, and roughly the same reactive components. The fundamental differences are how the topologies are controlled, and the relative size of the reactive components.

It is beyond the scope of this paper to provide a detailed design procedure for both topologies. However, it is worth taking a look at the results of our comparison.

Figure 7-3 shows two sets of graphs: one for the CLLLC and the other for the DAB. The plot on the left shows the RMS current in the GaN switch. The plot on the right shows the GaN FET drain-to-source voltage (V_DS) at turnon. These plots provide essential information on how efficient the switches will be in each topology. A low RMS current means fewer I²R losses, while a lower V_DS means lower switching losses. In the end, the highest efficiency will occur when the RMS currents are as small as possible and V_DS at turnon is as close to zero as possible.

Examining the plots in Figure 7-3 reveal that the CLLLC converter has lower RMS current when the output voltage is smaller. The reduced RMS current is critical to enabling the charger to put out as much power as possible at low voltages. Additionally, the CLLLC operates with more conditions where zero voltage switching (ZVS) is maintained.

These facts imply that the CLLLC converter will be more efficient, and therefore easier to cool. The CLLLC converter will also result in a smaller solution.

Raising the frequency of a switched-mode power supply results in a size reduction of many of the reactive components. The transformer is typically the largest single component in the DC/DC converter, and its physical size is highly dependent on operating frequency. The high efficiency of a GaN switch at elevated frequencies is the fundamental tool for reducing solution size.

Figure 8-1 shows how the operating frequency affects the transformer volume in a CLLLC converter. The transformer volume is normalized to the volume at 100 kHz, which means that at 500 kHz, the volume of the transformer should be about 35% of what a 100-kHz design would be. This enormous volumetric reduction means that designers will need to consider a few other factors before deciding on the exact switching frequency.

Controlling transformer core loss is a priority, especially high-frequency transformers. Equation 2, the Steinmetz equation, shows the relationship between loss density in the core and frequency:

where P_FE is the loss per unit volume; ƒ is the excitation frequency; B_PK is the peak flux density in the core; k, α and β are material constants.

From Equation 2, it is apparent that as the frequency increases, so will the losses. The losses in modern magnetic materials start to become difficult to manage when the switching frequency goes much above 1 or 2 MHz.