This document contains information for TPS6206x-Q1 (WSON package) to aid in a functional safety system design. Information provided are:

• Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
• Component failure modes and their distribution (FMD) based on the primary function of the device
• Pin failure mode analysis (Pin FMA)

Figure 1-1 shows the device functional block diagram for reference.

Figure 1-1 Functional Block Diagram

TPS6206x-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.

This section provides Functional Safety Failure In Time (FIT) rates for TPS6206x-Q1 based on an industry-wide used reliability standard:

• Table 2-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11.
• Table 2-2 provides FIT rates based on the Siemens Norm SN 29500-2

The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

• Mission profile: motor control
• Power dissipation: 300 mW
• Climate type: world-wide Table 8
• Package factor (lambda 3): Table 17b
• Substrate Material: FR4
• EOS FIT rate assumed: 0 FIT

The Reference FIT Rate and Reference Virtual T_J (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

The failure mode distribution estimation for TPS6206x-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS6206x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

• Pin short-circuited to PGND or AGND (see Table 4-2)
• Pin open-circuited (see Table 4-3)
• Pin short-circuited to an adjacent pin (see Table 4-4)
• Pin short-circuited to AVIN or PVIN (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Figure 4-1 shows the TPS6206x-Q1 pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TPS6206x-Q1 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

• Assumption the device is running in the typical application. Please refer to the 'Typical Application Circuit' on the 1st page in the TPS6206x-Q1 datasheet.