The TPS43340-Q1 is a quad rail power supply featuring two synchronous Buck Controller with 0.6-A gate drive, one synchronous 2-A Buck Converter and a 300-mA LDO with low quiescent current. The device is designed to power the entire system including MCU and DSP straight from the car battery respectively input voltages up to 40 V. The device features integrated short-circuit and overcurrent protection on the gate-drive outputs for the buck regulator controllers and independent current-foldback control for each buck regulator supply during regulator output short to ground. Each output supply incorporates a soft start to ensure that on initial power up these regulated outputs are not in current limit. Implementation of reset delay on power up allows the outputs of Buck1, Buck2, Buck3 and the linear regulator to get to stable regulation. An external capacitor sets the delay to a maximum range of 300 ms. Each power-supply output has adjustable output voltage based on the external resistor-network settings. The device has sequencing control during power up and power down of the output rails, based on the enable-and-disable control or soft start.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS43340-Q1 | HTQFP (48) | 7.00 mm × 7.00 mm |
Changes from D Revision (July 2015) to E Revision
Changes from C Revision (January 2013) to D Revision
Changes from B Revision (April 2012) to C Revision
Changes from A Revision (January 2012) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BOOT1 | 48 | I | A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck converter Buck1. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. |
BOOT2 | 37 | I | A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck converter Buck2. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. |
BOOT3 | 14 | I | A capacitor between BOOT3 and PH3 acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck converter Buck3. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. |
COMP1 | 8 | O | Error amplifier output of Buck1 and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the respective inductor. Clamping this voltage on the upper and lower ends provides current-limit protection for the external MOSFETs. |
COMP2 | 29 | O | Error amplifier output of Buck2 and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the respective inductor. Clamping this voltage on the upper and lower ends provides current-limit protection for the external MOSFETs. |
COMP3 | 18 | O | Error amplifier output of Buck3 and compensation node for voltage loop stability. The voltage at this node sets the target for the peak current through the respective inductor. |
EN1 | 22 | I | Enable input for Buck1. This input has an internal pullup with approximately 0.5 µA of current. |
EN2 | 21 | I | Enable input for Buck2. This input has an internal pullup with approximately 0.5 µA of current. |
EN3 | 20 | I | Enable input for Buck3. This input has an internal pullup with approximately 0.5 µA of current. |
EN4 | 47 | I | Enable input for LREG1 (active-high with an internal pullup current source). An input voltage higher than VIH enables the regulator, whereas an input voltage lower than VIL disables the regulator. This input has an internal pullup with approximately 0.5 µA of current. |
EXTSUP | 40 | I | One can use EXTSUP to supply the VREG regulator from one of theTPS43340 buck regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. When EXTSUP is open or lower than 4.6 V, VIN powers the regulator. If EXTSUP is unused, leave the pin open without a capacitor installed. |
GL1 | 3 | O | External low-side N-channel MOSFET gate drive for buck regulator Buck1. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin. |
GL2 | 34 | O | External low-side N-channel MOSFET for buck regulator This output can drive Buck2. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin. |
GND | 26 | O | Analog ground reference |
GPULL | 39 | O | Gate-driver output to implement the reverse-battery protection by an external PMOS. See the Application Information section for more details. |
GU1 | 1 | O | External high-side N-channel MOSFET gate drive for buck regulator Buck1. The output provides high peak currents to drive capacitive loads. The gate-drive reference is a floating-ground reference provided by PH1 and has a voltage swing provided by BOOT1. |
GU2 | 36 | O | This output can drive an external high-side N-channel MOSFET for buck regulator Buck2. The output provides high peak currents to drive capacitive loads. The gate-drive reference is a floating-ground reference provided by PH2 and has a voltage swing provided by BOOT2. |
LREG1 | 46 | O | Linear regulator output. Decouple with a low-ESR ceramic output capacitor in the range of 1 µF to 47 µF connected from this terminal to ground. |
PGND1 | 4 | O | Power ground connection for the GL1 driver. Connect to the source of the low-side N-channel MOSFET of Buck1. |
PGND2 | 33 | O | Power ground connection to the source of the low-side N-channel MOSFETs of Buck2 |
PGND3 | 12 | O | Buck3 power ground |
PH1 | 2 | O | Switching terminal of buck regulator Buck1, providing a floating ground reference for the high-side MOSFET gate-driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desirable. |
PH2 | 35 | O | Switching terminal of buck regulator Buck2, providing a floating ground reference for the high-side MOSFET gate-driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desirable. |
PH3 | 13 | O | Switching terminal of buck converter Buck3. Also provides a floating ground reference for the high-side MOSFET gate-driver circuitry |
Rdelay | 24 | O | The capacitor at the Rdelay pin sets the power-good delay interval used to de-glitch the outputs of the power-good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 μs, typical. |
RST1 | 9 | O | Open-drain power-good output for Buck1, with a 50-kΩ pullup resistor to S2. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls by RSTxth1 of the set value. |
RST2 | 28 | O | Open-drain power-good output for Buck2 with a 50 kΩ pullup resistor to S4. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls by RSTxth1 of the set value. |
RST3 | 16 | O | Open-drain power-good output for Buck3. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls by RSTxth1 of the set value. |
RST4 | 44 | O | Open-drain power-good indicator pin for LREG1, with a 50-kΩ pullup resistor to LREG1. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls by RSTxth1 of the set value. |
RT | 25 | O | Connecting a resistor to analog ground on this pin sets the operating switching frequency of the buck controllers and converter. Shorting this pin to ground or leaving it open defaults operation to 400 kHz for the buck controllers and the converter. |
S1 | 6 | I | High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for the buck controller. For details, see the Functional Description section. |
S2 | 5 | I | |
S3 | 31 | I | |
S4 | 32 | I | |
SLEW | 19 | I | Slew rate (dV/dt) selector of the internal high-side switching MOSFET for Buck3. For details, see the Application Information section. |
SS1 | 10 | O | Soft-start or tracking input for buck controller Buck1. The buck controller regulates the VSENSE1 voltage to the lower of 0.8 V or the SS1 pin voltage. An internal pullup current source of 1 μA is present at the pin, and use of an appropriate capacitor connected here can set the soft-start ramp duration. Alternatively, use of a resistor divider from another supply can provide a tracking input to this pin. |
SS2 | 27 | O | Soft-start or tracking input for buck controller Buck2. The buck controller regulates the VSENSE2 voltage to the lower of 0.8 V or the SS2 pin voltage. An internal pullup current source of 1 μA is present at the pin, and use of an appropriate capacitor connected here can set the soft-start ramp interval. Alternatively, use of a resistor divider from another supply can provide a tracking input to this pin. |
SS3 | 15 | O | Soft-start or tracking input for buck converter Buck3. The buck converter regulates the VSENSE3 voltage to the lower of 0.8 V or the SS3 pin voltage. An internal pullup current source of 1 μA is present at the pin, and an appropriate capacitor connected here can set the soft-start ramp duration. Alternatively, use of a resistor divider from another supply can provide a tracking input to this pin. |
SYNC | 23 | I | PLL synchronization, low-power mode-control pin. If an external clock is present on this pin, the device detects it and the internal PLL locks on to the external clock. This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. For details, see the Application Information section. |
VIN | 41 | I | Main Input pin. This is the buck controller and buck converter input pin. Additionally, it powers the internal control circuits of the device. Connect a bypass capacitor to filter noise between this pin and signal ground. |
VIN2SENSE | 43 | I | Supply-voltage sense input for the current mode of Buck2. Connect to the drain of the high-side-FET of Buck2. Cascading Buck1 as the supply for the Buck2 configuration does not support LPM on Buck2. |
VLR1 | 42 | I | The VLR1 terminal is the input voltage source for the linear regulator supply. This pin requires an input capacitor to ground to filter any noise present on the line. |
VREG | 38 | O | This pin requires an external capacitor to provide a regulated supply for the gate drivers of the buck controllers and converter. The regulator can obtain power either from VIN or EXTSUP. This pin has current limit-protection; do not use it to drive any other loads. |
VSENSE1 | 7 | I | Feedback voltage pin for Buck1. For details, see the Application Information section. |
VSENSE2 | 30 | I | Feedback voltage pin for Buck2. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage. |
VSENSE3 | 17 | I | Feedback voltage pin for Buck3. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage. |
VSENSE4 | 45 | I | Feedback voltage pin for linear regulator LREG1. LREG1 regulates the feedback voltage to the internal reference. A suitable resistor divider network between the LDO output and the feedback pin sets the desired output voltage. See the LREG1 parameters and the Application Information section. |
VSUP | 11 | I | Power supply for the Buck3 regulator. Provide good decoupling to PGND3 with a ceramic capacitor close to the pins. |
VALUE | UNIT | |||||
---|---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | All pins except VLR1 | ±2000 | V | |
VLR1 | ±1000 | |||||
Charged device model (CDM), per AEC Q100-011 | Corner pins (1, 12, 13, 24, 25, 36, 37, and 48) | ±750 | ||||
Other pins | ±500 | |||||
Machine model (MM) | All pins except RSTx | ±200 | ||||
RSTx | ±100 |
THERMAL METRIC(1) | TPS43340-Q1 | UNIT | |
---|---|---|---|
PHP (HTQFP) | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 26.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 12.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 7.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 7.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT SUPPLY | |||||||
VIN | Input voltage required for device on initial start-up | 6.5 | 40 | V | |||
Operating range after initial start-up | 4 | V | |||||
VIN UV | Undervoltage lockout | VIN falling. After a reset, initial start-up conditions may apply.(1) | 3.5 | 3.6 | 3.8 | V | |
VIN rising. After a reset, initial start-up conditions may apply.(1) | 3.8 | 4 | V | ||||
VLR1 | Device operating range for linear regulator | 4 | 40 | V | |||
IQ | Quiescent current | TA = 25°C | EN1 = 1, LPM; EN2,3,4 = 0 | 30 | 40 | µA | |
EN2 = 1, LPM; EN1,3,4 = 0 | 30 | 40 | |||||
EN4 = 1, LPM; EN1,2,3 = 0 | 48 | 60 | |||||
EN1,2 = 1, LPM; EN3,4 = 0 | 35 | 45 | |||||
EN3,4 = 1, EN1,2 = 0 | 4 | 4.5 | mA | ||||
TA = 125°C | EN1 = 1, LPM; EN2,3,4 = 0 | 40 | 50 | µA | |||
EN2 = 1, LPM; EN1,3,4 = 0 | 40 | 50 | |||||
EN4 = 1, LPM; EN1,2,3 = 0 | 52 | 60 | |||||
EN1,2 = 1, LPM; EN3,4 = 0 | 40 | 45 | |||||
EN3,4 = 1, EN1,2 = 0 | 5 | mA | |||||
IVIN | Quiescent current | TA = 25°C | VIN = 13 V, Buck1: CCM, Buck2: off, or VIN = 13 V, Buck2: CCM, Buck1: off, or VIN = 13 V, Buck1 and Buck2: CCM |
5 | mA | ||
TA = 125°C | Normal operation, SYNC = 5 V | 5 | mA | ||||
VIN = 13 V, Buck1: CCM, Buck2: off | 5 | ||||||
VIN = 13 V, Buck2: CCM, Buck1: off | 5 | ||||||
VIN = 13 V, Buck1, 2: CCM | 7 | ||||||
IVIN-SD | Shutdown current at TA = 25°C | EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V | 5 | 10 | µA | ||
IVIN-SD | Shutdown current at TA = 125°C | EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V | 20 | µA | |||
IVLRI-SD | Shutdown current at TA = 125°C | EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V | 5 | µA | |||
INTERNAL SUPPLY VREG | |||||||
VREG | Internal regulated supply | VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High | 5.5. | 5.8 | 6.1 | V | |
Load regulation | EXTSUP = 0 V, SYNC = High IVREG = 0 mA to 100 mA | 0.2% | 1% | ||||
VREG-EXTSUP | Internal regulated supply | EXTSUP = 8.5 V | 7.2. | 7.5 | 7.8 | V | |
Load regulation | EXTSUP = 8.5 V to 13 V, IVREG = 0 mA to 125 mA, SYNC = High | 0.2% | 1% | ||||
VEXTSUP-VREG | EXTSUP switch-over voltage | IVREG = 0 mA to 100 mA, EXTSUP ramping positive | 4.4 | 4.6 | 4.8 | V | |
VEXTSUP-HYS | EXTSUP switch-over hysteresis | 150 | 250 | mV | |||
IREG-LIM | Current limit on VREG | EXTSUP = 0 V normal mode as well as LPM | 100 | 400 | mA | ||
IREG-EXTSUP-LIM | Current limit on VREG when using EXTSUP | IVREG = 0 mA to 100 mA, EXTSUP = 8.5 V, SYNC = High | 125 | 400 | mA | ||
INPUT VOLTAGE VIN - OVERVOLTAGE LOCK OUT AND REVERSE POLARITY PROTECTION | |||||||
VOVLO | Overvoltage shutdown | VIN rising | 45 | 46 | 47 | V | |
VIN falling | 43 | 44 | 45 | V | |||
OVLOHys | Hysteresis | 1 | 2 | 3 | V | ||
OVLOfilter | Filter time | 5 | µs | ||||
VGD | Clamping voltage of ext. FET | VIN - GPULL | 17 | V | |||
RGPULL | Internal resistance to GND | 500 | kΩ | ||||
BUCK CONTROLLERS | |||||||
VOUT1, VOUT2 | Adjustable output voltage range | 0.9 | 11 | V | |||
VREF | Internal reference voltage and tolerance in normal mode | Measure VSENSEx pin | 0.792 | 0.8 | 0.808 | V | |
–1% | 1% | ||||||
VREF, LPM | Internal reference voltage and tolerance in low-power mode | Measure VSENSEx pin | 0.784 | 0.8 | 0.816 | V | |
–2% | 2% | ||||||
VSENSE | VSENSE for forward-current limit in CCM | VSENSEx = 0.75 V, duty cycles < 10% | 60 | 75 | 90 | mV | |
VSENSE for reverse-current limit in CCM | VSENSEx = 1 V | –65 | –37.5 | –23 | mV | ||
VI-Foldback | VSENSE for output short | VSENSEx = 0 V (foldback) | 17 | 43.8 | 48 | mV | |
tdead | Shoot through delay, blanking time | 20 | ns | ||||
DCNRM | High-side minimum on-time | 100 | ns | ||||
Maximum duty cycle (digitally controlled) | 98.75% | ||||||
DCLPM | Duty cycle LPM | 80% | |||||
ILPM_Entry | LPM entry threshold load current as fraction of maximum set load current | 1% | |||||
VLPM_Exit | LPM exit threshold load current as fraction of maximum set load current | 10% | |||||
HIGH-SIDE EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLERS | |||||||
IGUx_peak | Gate driver peak current | 0.6 | A | ||||
rDS(on) | Source and sink driver | VREG = 5.8 V, IGUx current = 200 mA | 5 | Ω | |||
LOW-SIDE NMOS GATE DRIVERS FOR BUCK CONTROLLERS | |||||||
IGLx_peak | Gate driver peak current | 0.6 | A | ||||
rDS(on) | Source and sink driver | VREG = 5.8V, IGLx current = 200 mA | 5 | Ω | |||
INTERNAL OSCILLATOR (RT) | |||||||
fSW | Buck switching frequency | RT pin: GND | 360 | 400 | 440 | kHz | |
fSW | Buck switching frequency | RT pin: 60 kΩ external resistor | 360 | 400 | 440 | kHz | |
fSW-adj | Buck adjustable range with external resistor | RT pin: external resistor | 150 | 600 | kHz | ||
fsync | Buck synch. range | External clock input on SYNC | 150 | 600 | kHz | ||
VRT | Oscillator reference voltage | 1.2 | V | ||||
tSW-Prop dly | SYNC rising edge to PH rising edge delay | 0 | 20 | 40 | ns | ||
tSW-Trans-delay | Last SYNC rising edge to return to resistor mode if CLK is not present on SYNC pin | 20 | µs | ||||
ERROR AMPLIFIER (OTA) FOR BUCK CONTROLLERS AND BUCK CONVERTER | |||||||
IPULLUP_VSENSEx | Pullup current at VSENSEx pins | VSENSEx = 0 V | 50 | 100 | 200 | nA | |
gm | Forward transconductance | COMP1, COMP2 = 0.8 V; source/sink = 5 µA, Test in feedback loop | 0.7 | 0.9 | 1.35 | mS | |
EXTERNAL CLOCK AND ENABLE INPUTS: SYNC. EN1, EN2, EN3, EN4 | |||||||
VIH | Higher threshold | VIN = 13 V | 1.7 | V | |||
VIL | Lower threshold | VIN = 13 V | 0.7 | V | |||
RIH | Pulldown resistance | VSYNC = 5 V | 500 | kΩ | |||
IIL_ENx | Pullup current | VENx = 0V | 0.5 | 2 | µA | ||
tdeglitch | Deglitch time, ENx | 2 | 16 | µs | |||
LINEAR REGULATOR LREG1 | |||||||
VLREG1 | Regulated output range | IL = 10 µA to 300 mA | 0.8 | 5.25 | V | ||
VREF | Internal reference voltage tolerance | Referred to 0.8-V VREF, measured at VSENSE4 | –2.5% | 2.5% | |||
Vline-reg | Line regulation | VIN = VLR1: 6 V to 28 V, IOUT 4 = 10 mA, | ∆VOUT, VOUT = 5 V | 15 | mV | ||
∆VOUT, VOUT = 3.3 V | 15 | ||||||
∆VOUT, VOUT = 1.5 V | 15 | ||||||
Vload-reg | Load regulation | IOUT4 = 10 mA to 300 mA, VIN = 14 V | ∆VOUT, VOUT = 5 V | 10 | mV | ||
∆VOUT, VOUT = 3.3 V | 10 | ||||||
∆VOUT, VOUT = 1.5 V | 10 | ||||||
VDropout | Drop out voltage | VIN = VLR1 = 4 V: IOUT = 250 mA | 500 | mV | |||
VIN = 9 V, VLR1 = 4 V: IOUT = 150 mA | 300 | ||||||
IOUT4 | Output current | VOUT in regulation | 0.01 | 300 | mA | ||
ILREG1-CL | Output current limit | VOUT = 0 V | 400 | 1000 | mA | ||
dVLREG1 / dt | Output soft start slew rate | 5 | V/ms | ||||
PSRR | Power supply ripple rejection | Vripple = 0.5 VPP, IOUT = 300 mA | Freq = 100 Hz | 60 | dB | ||
Freq = 150 kHz | 25 | ||||||
VTH-CP ONp | Charge-pump turnoff voltage, VIN rising | 9.4 | V | ||||
Hysteresis | 0.18 | V | |||||
ITH-CP-OFF | Low-load current-detection threshold | IOUT4 falling | 2 | mA | |||
Low-load current-detection hysteresis | 4 | mA | |||||
SOFT START SSX | |||||||
ISSx | Soft-start source current | SSx = 0 V | 0.75 | 1 | 1.25 | µA | |
RESET RSTx | |||||||
RSTpullup | RST1 to S2, RST2 to S4, RST4 to LREG1 internal pullups | 50 | kΩ | ||||
RSTxth1 | Reset threshold | VSENSEx falling | –5 | –7 | –9.5 | %VREF | |
RSTxhys | Hysteresis | 2 | %VREF | ||||
RSTxdrop | Voltage drop | IRSTx = 5 mA | 450 | mV | |||
IRSTx = 1 mA | 100 | mV | |||||
RSTxleak | Leakage | VS2 = VS4 = VRSTx = 13 V, RST4 = 8 V | 1 | µA | |||
tdeglitch | Power-good deglitch time | 2 | 16 | µs | |||
tdelay | Reset release delay | External capacitor = 1 nF | 1 | ms | |||
tdelay_fix | Fixed reset delay | No external capacitor, Rdelay pin open | 20 | 50 | µs | ||
IOH | Activate current source (current to charge external capacitor) | Current to charge external capacitor | 30 | 40 | 50 | µA | |
IIL | Activate current sink (current to discharge external capacitor) | Current to discharge external capacitor | 30 | 40 | 50 | µA | |
SYNCHRONOUS BUCK CONVERTER BUCK3 | |||||||
VSUP | Buck3 supply voltage | 4 | 10 | V | |||
VSUP_UV | Buck3 undervoltage lockout | VSUP falling | 3.6 | 3.7 | 3.8 | V | |
VSUP rising | 3.7 | 3.8 | 3.9 | V | |||
rDS(on) | High-side switch | VSUP = 9 V, VBoot3 –PH3 = 5.8 V | 0.14 | 0.28 | Ω | ||
Low-side switch | VSUP = 9 V, VVREG-PGND3 = 5.8 V | 0.15 | 0.28 | Ω | |||
IHS-Limit | High-side switch | 2.5 | A | ||||
ILS-Limit | Low-side switch, current into PH3 | 2.38 | A | ||||
VSUPLkg | VSUP leakage current | VSUP = 10 V for high side, EN3 = Low. TJ = 100°C | 1 | µA | |||
IFB3 | Current foldback | VSENSE3 = 0 V | 1.9 | A | |||
fSW-adj | Buck3 switching frequency range with external resistor | Using external resistor on RT/CLK | 150 | 600 | kHz | ||
VSense | Feedback voltage | Internal ref = 0.8 V | –1.5% | 1.5% | |||
fSW-f-back | 2-times - frequency foldback exit threshold, VSENSE3 rising | 0.65 | V | ||||
2-times - frequency foldback entry threshold, VSENSE3 falling | 0.6 | V | |||||
Gm3 | Current loop transconductance | ΔIpeakPH3 / ΔVCOMP3 | 5.4 | S | |||
DC3 | Minimum duty cycle | fSW = 400 kHz, SLEW = LOW or OPEN | 10% | ||||
Maximum duty cycle | In dropout operation | 98.75% | |||||
TOT-BUCK3 | Overtemperature sensor threshold, leads to Buck3 FET deactivation | 170 | °C | ||||
TOT-BUCK3-HYS | Overtemperature sensor hysteresis | 15 | °C | ||||
THERMAL SHUTDOWN | |||||||
Tshutdown | Junction temperature shutdown threshold | 150 | 170 | °C | |||
Thys | Junction temperature hysteresis | 15 | °C |
VIN = 12 V | VOUTx = 5 V | RSENSE = 10 mΩ |
Inductor = 4.7 µH | Switching Frequency = 400 kHz |
VIN = 12 V | VOUTx = 5 V | RSENSE = 10 mΩ |
Inductor = 4.7 µH | Switching Frequency = 400 kHz | |
VSUP = 4, 5, OR 6 V | Inductor = 10 µH | VSENSE3 = 0.75 V | ||
Switching Frequency = 400 kHz |
VIN = 14 V | VOUT = 3.3 V | VSUP = 4 V |
VIN = 12 V | VOUTx = 5 V | RSENSE = 10 mΩ |
Inductor = 4.7 µH | Switching Frequency = 400 kHz |
The TPS43340-Q1 is a dual-buck regulator controller (Buck1, Buck2), single-buck regulator converter (Buck3) and linear regulator (LREG1) designed for powering the Texas Instruments family of DSPs and microcontrollers or general-market MCU products. The device features integrated short-circuit and overcurrent protection on the gate-drive outputs for the buck regulator controllers and independent current-foldback control for each buck regulator supply during regulator output short to ground. Each output supply incorporates a soft start to ensure that on initial power up these regulated outputs are not in current limit. Implementation of reset delay on power up allows the outputs of Buck1, Buck2, Buck3 and the linear regulator to get to stable regulation. An external capacitor sets the delay to a maximum range of 300 ms. Each power-supply output has adjustable output voltage based on the external resistor-network settings. The device has sequencing control during power up and power down of the output rails, based on the enable-and-disable control or soft start.
The use of independent enable inputs at the EN1 through EN4 pins enables all the regulators. These pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on any of these pins enables its respective regulator. EN1, EN2, and EN4 are high-voltage pins, which permits their connection directly to the battery for self-bias. When all regulators are disabled, the device shuts down and consumes a current of 5 µA typical.
The linear regulator is an NMOS output low-dropout regulator with output load current up to 300 mA. It can operate directly from the battery. With EN4 tied high or open, LREG1 turns on its output following an internally generated soft-start ramp. The regulation loop uses internal frequency compensation. If the output shorts to ground, the device protects itself by limiting the current. For VIN lower than 9 V, LREG1 controls the internal charge pump depending on VIN and the load current in accordance with Table 4. An internal voltage selector selects the higher available supply, VIN or the charge pump voltage, for the error amplifier. The device monitors the output voltage of the low-dropout regulator for undervoltage and signals its state on pin RST4.
An internal linear regulator supplies the gate drivers of the buck controllers and the buck converter. The regulator output (5.8 V typical) is available at the VREG pin and requires decoupling using a ceramic capacitor in the range of 3.3 µF to 10 µF. This pin has an internal current-limit protection; do not use it to power any other circuits.
Power for the VREG linear regulator comes from VIN by default when the EXTSUP voltage is lower than 4.6 V (typical). Should there be an expectation of VIN going to high levels, there can be excessive power dissipation in this regulator, especially at high switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin, connection to which can be to a supply lower than VIN but high enough to provide the gate drive. The voltage on EXTSUP should not exceed 9 V. With EXTSUP connected to a voltage greater than 4.6 V, the linear regulator automatically switches to EXTSUP. Efficiency improvements are thus possible when using one of the switching regulator rails from the TPS43340-Q1 or any other voltage available in the system to power the EXTSUP. If the EXTSUP supply is above 4.6 V but below 7.5 V, the EXTSUP-LDO acts as a pass element, providing EXTSUP voltage less a small dropout to VREG.
Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as it provides a large gate drive and hence better on-resistance of the external MOSFETs.
When using EXTSUP, always keep the buck rail supplying EXTSUP enabled. Alternatively, if it is necessary to switch off the buck rail supplying EXTSUP, place a diode between the buck rail and EXTSUP.
During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.
The TPS43340-Q1 includes a gate driver for an external P-channel MOSFET which can be used for reverse battery protection. This is useful to reduce the voltage drop across the protection element compared to using a series diode to VIN. The gate – source voltage of the external PMOS is clamped by an internal Zener diode to
17 V typical.
VBAT ≤ VF → | VGS | = 0 V → FET and diode not conducting VF ≤ VBAT ≤ VT (FET) → | VGS | = VBAT → FET NOT conducting and diode conducting VT (FET) ≤ VBAT ≤ 17 V → | VGS | = VBAT → FET conducting VBAT ≥ 17 V → | VGS | = 17 V → FET conducting |
Spacer
NOTE
An implementation without the PMOS blocks the current coming from Buck-outputs (improper OR-ing, and others), which may result in exceeding the absolute maximum ratings.
The TPS43340-Q1 starts up at a VIN voltage of 6.5 V (maximum). Once it has started up, the device operates down to a VIN undervoltage lockout level of 3.6 V or until reaching a VREG undervoltage of 3.6 V. A voltage above 46 V at VIN shuts down the device. In order to prevent transient spikes from shutting down the device, the under- and overvoltage protection have filter times of 5 µs (typical). There is no support for overvoltage protection in LPM.
When the voltages return to the normal operating region, the enabled regulators start up with a soft-start ramp.
This regulator operates with the switching frequency set on the RT terminal or an external clock input on the SYNC terminal. The internal power FETs switch out of phase to regulate the output voltage, operating in a pulse width modulation. The converter uses a peak-current mode-control loop with external frequency compensation. The synchronous operation mode improves the overall efficiency.
A capacitor on the SS3 terminal sets the converter soft start. Pulling the enable pin on EN3 high activates soft start. During soft start or whenever the voltage on VSENSE3 falls below limits given by ƒSW-f-back, the converter switches to a frequency foldback of ƒsw / 2 to help control the coil current. In addition to the frequency foldback, implementation of current foldback reduces power dissipation to protect the converter against an output short to ground. Like in the buck controllers, the current foldback reduces the maximum peak current limit depending on the voltage on the VSENSE3 pin. Figure 9 shows the characteristic of current foldback.
Measurement of the coil peak current is by use of the high-side integrated FET; peak-current regulation occurs in each switching cycle in accordance with the voltage on the COMP3 pin. COMP3 is the output of a transconductance error amplifier of the voltage feedback loop for Buck3, as COMP1 and COMP2 are for controllers Buck1 and Buck2. COMP3 sets the target for the peak current comparator (inner current loop) and serves as frequency compensation of the voltage loop using a type II compensation network.
Clamping the voltage on the COMP3 node realizes the positive current limit. The positive clamping level depends on the voltage on the VSENSE3 pin, as described previously. The device also implements clamping for low voltage on the COMP3 pin, thereby speeding up the transient response after output overshoot. For stability of the current loop, during the switching cycle the internal slope compensation adjusts the current limit set by COMP3.
For correct operation of the slope compensation, the coil used for Buck3 must satisfy the following:
where
Reaching the positive current limit during the high PWM phase resets the PWM. The high-side FET turns off and the low part of the cycle is initiated. On detecting an overcurrent condition such as an output short to a supply during the PWM low phase, the low-side FET turns off until the end of the given cycle, to allow the coil current to flow through the body diode of the high-side FET.
This converter is capable of operating with a low input-to-output voltage difference. In dropout operation, the integrated high-side MOSFET stays on continuously. In every fourth clock cycle, the device limits the duty cycle to 95% in order to charge the bootstrap capacitor at BOOT3. This allows a maximum duty cycle of 98.75% for the buck converter. In this mode, the output tracks the input until initiation of the internal undervoltage lockout due to low supply voltage on the VSUP pin.
Thermal shutdown monitors the virtual junction temperature of the integrated FETs. When TJ exceeds 170°C, both the high- and low-side switches turn off. The converter returns to normal operation when the temperature decreases to the acceptable level (typically TJ = 150°C)
The setting on the SLEW terminal controlss the slew for Buck3. Setting the slew rate to logic high (slowest slew rate) extends the minimum on-time of the buck converter by 5% of the clock period.
SLEW TERMINAL SETTING | tr (TYP) ns | tf (TYP) ns |
---|---|---|
SLEW > VREG – 0.2 V (low slew rate, logic high) | 24 | 7 |
SLEW pin open – medium slew rate | 11 | 3 |
SLEW < 0.2 V (fast slew rate, logic low) | 8 | 2 |
The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending on the resistor value at the RT pin. Tying this pin to ground sets the default switching frequency to 400 kHz. A resistor connected to RT can also set the frequency according to the formula:
where
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz. The device detects clock pulses at this pin, and an internal PLL locks onto the external clock within the specified range. The device can also detect a loss of clock at this pin, and detection of clock loss for tSW-Trans-delaysets the switching frequency to the internal oscillator. The two buck controllers operate at the same switching frequency, 180 degrees out of phase.
Choose the resistor feedback divider networks connected to the VSENSEx (feedback) pins to set the output voltages. Make the choice such that the regulated voltages at the VSENSEx pins equal 0.8 V. The VSENSEx pins have 100-nA pullup current sources as a protection feature in case the pins open up as a result of physical damage.
In order to avoid large inrush currents, both buck controllers have independent programmable soft-start timing. The voltage at the SSx pins acts as the soft-start reference voltage. A 1-µA pullup current is available at the SSx pins, and by choosing a suitable capacitor one can obtain a desired soft-start ramp speed. After start-up, the pullup current ensures that pins SSx are higher than the internal reference of 0.8 V, which then becomes the reference for the buck controllers. The required capacitor for ∆t, the desired soft-start time, is given by:
where
Alternatively, one can use the soft-start pins as tracking inputs. In this case, connect the pins to the supply to be tracked via a suitable divider network.
Peak current-mode control regulates the peak current through the inductor such that the output voltage maintains its set value. The error between the feedback voltage at VSENSEx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as the target for the peak inductor current. This target provides a comparison for the current through the inductor, sensed as a differential voltage at S1-S2 for Buck1 and S3-S4 for Buck2, and compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at VSENSEx, causing COMPx to fall or rise, respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. In this way, the device maintains the output voltage in regulation.
The high-side N-channel MOSFET turns on at the beginning of each clock cycle and remains on until the inductor current reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay), the lower N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET stays on continuously. In every fourth clock cycle, the duty cycle is limited to 95% in order to charge the bootstrap capacitor at BOOTx. This allows a maximum duty cycle of 98.75% for the buck regulators. Thus, during dropout the buck regulators switch at one-fourth of the normal frequency.
Clamping the maximum value of COMPx is such as to limit the maximum current through the inductor to a specified value. When the output of the buck regulator (and hence the feedback value at VSENSEx) falls to a low value due to a short circuit or overcurrent condition, the clamping voltage at the COMPx successively decreases, thus providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-direction current limit).
Similarly, if due to a fault condition the output shorts to a high voltage and turns the low-side MOSFET fully on, the COMPx node drops low. The device holds COMPx at a low level as well in order to limit the maximum current in the low-side MOSFET (reverse direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This value specification is at low duty cycles only. At typical duty cycle conditions around 40% (assuming 5-V output and 12-V input), 50 mV is a more reasonable value, considering the slope compensation and tolerances. The typical characteristics in Figure 18 and Figure 12 provide a guide for using the correct current-limit sense voltage.
The current-sense pins Sx are high-impedance pins with low leakage across the entire output range. These pin characteristics allow DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 17 shows DCR sensing. Here the series resistance (DCR) of the inductor serves as the sense element. Place the filter components close to the device for noise immunity. Remember that while DCR sensing gives high efficiency, it is less accurate due to the temperature sensitivity and a wide variation of the parasitic series resistance of the inductor. Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.
Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable current-mode operation in all conditions. For optimal performance of this circuit, satisfy the following condition in the choice of inductor and sense resistor:
where
Each buck controller has an independent reset comparator monitoring the feedback voltage at the VSENSEx pins and indicating whether the output voltage has fallen below the specified reset threshold. The reset indicator is available as an open-drain output at the RSTx pins. An internal 50-kΩ pullup resistor to S2 or S4 is available, or one can use an external resistor. When a buck controller shuts down, the device pulls down the power-good outputs internally. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow through the resistor when the buck controller powers down.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the device implements an internal delay of tdeglitch for de-glitching. The output voltage reaching its set value after a start-up ramp or negative transient asserts the power-good indicator high (releases the open-drain pin) after a delay of tdelay, at least tdelay_fix. A use of this is to delay the reset to the circuits being powered from the buck regulator rail. Program the delay of this circuit by using a suitable capacitor at the Rdelay pin according to Equation 6:
Power-Good Output Delay
where
An open on the Rdelay pin sets the delay to a default value of 20 µs typical. The power-good delay timing is common to all supply rails, but the power good comparators and outputs function independently.
An external clock or a high level on the SYNC pin or enabling Buck3 results in forced continuous-mode operation of the bucks. Having the SYNC pin low or open allows the buck controllers to operate in discontinuous mode at light loads by turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side and the low-side MOSFETs are turned off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VIN > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1% of the set full-load current if the choice of the inductor and the sense resistor is appropriate as recommended in the slope compensation section.
In low-power PFM mode, the buck controllers monitor the VSENSEx voltage and compare it with the 0.8 V internal reference. Whenever the VSENSEx value falls below the reference, the high-side MOSFET turns on for a pulse-duration inversely proportional to the difference across VIN-S2 for Buck 1 and VIN-S4 for Buck2. At the end of this on-time, the high-side MOSFET turns off and the current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the next time VSENSEx falls below the reference value. This results in a constant volt-second TON hysteretic operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and 35 µA when both channels are active.
As the load increases, the pulse become more and more frequent until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion for exit from the low-power mode is when VIN falls low enough to require a higher-than-80% duty cycle of the high-side MOSFET.
The TPS43340-Q1 can support the full-current load during low-power mode until the transition to normal mode takes place. The design ensures the low-power-mode exit occurs at 10% (typical) of full-load current if the inductor and sense resistor choices are as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for entry to low-power mode.