This user’s guide can be used as a guide for integrating the TPS6594-Q1 power management integrated circuit (PMIC) into a system powering the industrial AM65x Sitara™ processor.
Sitara™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
This user’s guide describes a power distribution network (PDN) using a TPS6594-Q1 device to supply the AM65x processor with independent MCU and Main power rails. This PDN enables board level isolation of the MCU safety island and main voltage resources as required for implementing two desirable features of the processor:
The following topics are described to clarify platform system operation:
There are different orderable part numbers (OPNs) of the TPS6594-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1.
Features Supported | Orderable Part Number | TI_NVM_ID | TI_NVM_REV |
---|---|---|---|
|
TPS65941319RWERQ1 | 0x19 | 0x01 |