LMK03318 Ultra-Low-Noise Jitter Clock Generator Family With One PLL, Eight Outputs, Integrated EEPROM

1 Features

Ultra-Low Noise, High Performance
- Jitter: 100-fs RMS Typical, F_OUT> 100 MHz
- PSNR: –80 dBc, Robust Supply Noise Immunity
Flexible Device Options
- Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination
- Pin Mode, I²C Mode, EEPROM Mode
- 71-Pin Selectable Pre-programmed Default Start-Up Options
Dual Inputs With Automatic or Manual Selection
- Crystal Input: 10 to 52 MHz
- External Input: 1 to 300 MHz
Frequency Margining Options
- Fine Frequency Margining Using Low-Cost Pullable Crystal Reference
- Glitchless Coarse Frequency Margining (%) Using Output Dividers
Other Features
- Supply: 3.3-V Core, 1.8-V, 2.5-V, or 3.3-V Output Supply
- Industrial Temperature Range (–40ºC to 85ºC)

2 Applications

Switches and Routers
Network and Telecom Line Cards
Servers and Storage Systems
Wireless Base Station
PCIe Gen1, Gen2, Gen3, Gen4
Test and Measurement
Broadcast Infrastructure

3 Description

The LMK03318 device is an ultra-low-noise PLLATINUM™ clock generator with one fractional-N frequency synthesizer with integrated VCO, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, thus reducing BOM cost and board area and improving reliability by replacing multiple oscillators and clock distribution devices. The ultra-low jitter reduces bit-error rate (BER) in high-speed serial links.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LMK03318	WQFN (48)	7.00 mm × 7.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.