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This document contains information for the LM4050-N-Q1 (SOT-23 package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
The LM4050-N-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides functional safety failure in time (FIT) rates for the LM4050-N-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total component FIT rate | 4 |
Die FIT rate | 3 |
Package FIT rate | 1 |
The failure rate and mission profile information in Table 2-1 comes from the reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
5 | CMOS, BICMOS Digital, analog, or mixed | 20 FIT | 55°C |
The reference FIT rate and reference virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for the LM4050-N-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
VR voltage accuracy outside of the specifications | 40 |
VR does not meet dynamic impedance specification | 20 |
Minimum regulation current exceeds maximum value of the specification | 40 |
This section provides a failure mode analysis (FMA) for the pins of the LM4050-N-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality. |
B | No device damage, but loss of functionality. |
C | No device damage, but performance degradation. |
D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the LM4050-N-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the LM4050-N-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
---|---|---|---|
Cathode | 1 | The output does not regulate and cathode pin is held low. | B |
Anode | 2 | No effect to functionality; the device is operating as intended. | D |
NC | 3 | No effect to device functionality. | D |
Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
---|---|---|---|
Cathode | 1 | The device is unpowered. | B |
Anode | 2 | The output does not regulate and is held low. | B |
NC | 3 | No effect to device functionality. | D |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
---|---|---|---|---|
Cathode | 1 | Anode | The output does not regulate and cathode pin is held low. | B |
Anode | 2 | NC | No effect to device functionality. | D |
NC | 3 | Cathode | Not recommended connection. Iq can increase. | C |
Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
---|---|---|---|
Cathode | 1 | No effect to device functionality; the device is operating as intended. | D |
Anode | 2 | The output does not regulate. The cathode pin is held low. | B |
NC | 3 | Not recommended connection. Iq can increase | C |