SNVA881 November 2019 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1 , LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
This application report provides an overview of recommended parameters for LP8756x-Q1 and LP8752x-Q1 devices considering stability. Recommendations are based on real measurement data as well as simulations. For more information about LP8756x-Q1 and LP8752x-Q1 devices, refer to the product web pages LP87561-Q1, LP87562-Q1, LP87563-Q1, LP87564-Q1, LP87565-Q1 and LP87523-Q1.
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The LP8756x-Q1 and LP8752x-Q1 devices are designed to meet the power-management requirements of the latest processors and platforms in various automotive power applications. Both devices contain four stepdown DC/DC converter cores, which are configured as a 4-phase output, 3-phase and 1-phase outputs, 2-phase and 2-phase outputs, one 2-phase and two 1-phase outputs, or four 1-phase outputs. The devices are controlled by an I2C-compatible serial interface and by enable signals.
The automatic pulse-width-modulation (PWM) to pulsed-frequency-modulation (PFM) operation (AUTO mode) and the automatic phase adding and phase shedding maximizes efficiency over a wide output-current range. The LP8756x-Q1 and LP8752x-Q1 support remote differential-voltage sensing for multiphase outputs, which compensates the IR drop between the regulator output and the point-of-load (POL), improves the accuracy of the output voltage. The switching clock can be forced to the PWM mode and also synchronized to an external clock to minimize the disturbances.
LP8756x-Q1 and LP8752x-Q1 supports the load-current measurement without additional external current sense resistors. The devices also support programmable start-up and shutdown delays and sequences synchronized to enable signals. The sequences can include GPIO signals to control external regulators, load switches, and processor reset. During start-up and voltage change, the devices control the output slew rate to minimize an output voltage overshoot and in-rush current.
This application report can be used as a reference in selecting external components and phase configuration to achieve the wanted phase margin. This application report does not provide information about the electrical characteristics, package, or the functionality of the device. For this information and the full register maps, refer to LP8756x-Q1 16-A Buck Converter With Integrated Switches and LP8752x-Q1 10-A Buck Converter With Integrated Switches datasheets.
The loop is stable when the system's feedback is negative and limits the gain. In other words, the loop is unstable if the negative feedback turns into positive feedback, which consequently saturates the output to supply limits. Negative feedback will turn in to positive feedback if the phase changes by 180 degrees and the closed loop gain is positive. The frequency is the point of interest in the measurements where the phase crosses 0 or ±180 degrees and the gain falls below 0 dB (the gain and phase margin is measured from those frequencies). The gain margin defines how much more gain the loop may have until it becomes unstable, and the phase margin defines how much phase shift there may be until the loop becomes unstable.
Generally the loop has sufficient stability margin if it has over 45 degrees of phase margin and over 10 dB of gain margin (these are often the design targets). Even the lower margins and theoretically the loop are stable, if both the gain and phase margins are larger than 0 dB or 0 degrees, but 10 dB gain margin and 45 degree phase margin are considered a standard safety buffer for stability. Higher stability margins are possible at the expense of slower transient response. For the LP8756x-Q1 and LP8752x-Q1 devices, the phase margin of 45 degrees and 10 dB gain margin are a good compromise between stability and transient response. Many different parameters affect both the phase and gain margin, and this application report focuses on systematically iterating through some of the most significant parameters. Layout has an impact on phase margin as well, but iterating through multiple different layouts was not possible. To maximize the phase margin, the PCB parasitic inductance should be minimized and the point of load capacitors should be placed as close to the load as possible. For more information about phase margin and closed loop stability, refer to Switch-mode power converter compensation made easy article.
Please note that the inductor value should be kept at a constant 470 nH, as the internal compensation of the device is configured for previously mentioned inductance. The device verification and validation has been done using 470 nH inductors.
General use cases for the LP875x-Q1 devices are listed in Table 1. The total output capacitance is the sum of the CLOCAL capacitance near the switcher and CPOL point of load (POL) capacitance. The maximum total output capacitance per phase is 500 µF, if the output voltage slew-rate is less than or equal to 1.9 mV/µs. Higher slew-rates have lower maximum capacitance limits. Refer to LP8756x-Q1 16-A Buck Converter With Integrated Switches or LP8752x-Q1 10-A Buck Converter With Integrated Switches datasheet for more information.
VIN (V) | Switching frequency (MHz) | L (nH) | CIN (µF/phase) | VOUT (mV) | CLOCAL (µF/phase) | IOUT (A) | CPOL (µF/phase) |
---|---|---|---|---|---|---|---|
3.3 | 2 | 470 | 10 | 860 | 22 | 3.0 | 22 |
44 | |||||||
91 | |||||||
5.0 | 22 | ||||||
44 | |||||||
91 | |||||||
3.3 | 1000 | 22 | |||||
44 | |||||||
91 | |||||||
5.0 | 22 | ||||||
44 | |||||||
91 | |||||||
3.3 | 1800 | 22 | |||||
44 | |||||||
91 | |||||||
5.0 | 22 | ||||||
44 | |||||||
91 | |||||||
5.0 | 3300 | 22 | |||||
44 | |||||||
91 |
In addition to the 21 use cases listed in Table 1, the phase configuration has an effect on stability. Every use case is measured and simulated for every phase configuration from 1 to 4 phases, totaling 84 measurements and simulations.