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The increasing popularity of embedded systems in a wide range of applications pushes for a higher level of integration onto a single SoC. This high level of integration leads to higher power dissipation, increased thermal system cost, degraded performance, and reduced battery life. To overcome these challenges, SoCs should be defined, architected, and designed in the context of their usage in the targeted embedded systems. Since every application is different, picking the correct operating settings for the SoC will achieve optimal performance and power. This paper presents novel features and techniques developed on the AM62x processors - a next-generation Sitara MPU device from Texas Instruments.
AM62x processors feature a high-performance Quad-core Cortex A53 with 64-bit architecture, a powerful 3D Graphics Engine, an integrated M4F MCU Channel for general purpose usage or safety with full freedom-from interface (FFI) from the application domain, a Dual-core M4F for Foundational and Automotive/Industrial Security, a dedicated R5F core for device resources and low power management. The modular architecture of this device delivers performance with support for several low power modes without sacrificing critical system resources, such as connectivity, power, security, safety, and cost. Figure 1 shows a high-level AM62x processor block diagram.
The AM62 processor uses several essential techniques to reduce active and static power consumption. Table 2-1 shows the AM62x power management features and the benefits.
Key Features | AM62x Power Management | Benefits |
---|---|---|
Low Power Modes | DeepSleep, MCU Only, Standby, Partial I/O | Longer battery operation lifetime |
Active Power Management | Low bus clock frequency operation at 125 MHz (OPP low) | Low active power consumption for low activity use cases |
Dynamic frequency scaling (DFS) | Thermal management | |
Power Supply Simplification |
Up to 1.25 GHz A53 at 0.75 V Up to 1.4 GHz A53 at 0.85 V |
Differentiated low power capability with 0.75-V core power supply Higher performance with 0.75-V core power supply |
Single core power supply Simpler power domains |
Lower cost power solution and less complicated software control for power management | |
Simple power sequencing with integrated LDO enabling a low-cost discrete power solution |
Easier to optimize a power solution for the overall system Low-cost power solution |
|
Companion PMIC | New low cost PMIC | Low cost PMIC optimized for AM62x |
The AM62x processor supports optimized low power modes with varying levels of power dissipation: Partial I/O mode to Deepsleep mode to Standby mode (sub mW to a few mW). Table 2-2 shows a high-level description of various low-power modes supported on AM62x processors.
Low Power Modes | Wakeup Sources | Application State and Use Case |
---|---|---|
Partial I/O | CANUART I/O Bank pins | The entire SoC is OFF except I/O pins in CANUART I/O bank to maintain I/O wakeup capability from CANUART I/O Bank I/O pins. |
DeepSleep | GP Timers, RTC Timer, UART, I2C, MCU GPIO0, I/O Daisy Chain, USB wakeup events | Core domain register information will be lost. On-chip peripheral register (context) information of core domain needs to be saved by application to DDR before entering this mode. DDR is in self-refresh. Boot ROM executes and branches to peripheral context restore for wakeup, followed by system resume. This mode is primarily used for Suspend to RAM for battery lifetime or backup operation. |
MCU Only | DeepSleep wakeup events, Interrupt evens supported in MCU channel | The MCU subsystem runs at the MCU PLL clock. The rest of the SoC status is the same as DeepSleep. DDR is in self-refresh. MCU can run applications with MCU domain peripherals while in this low power mode. |
Standby | Any SoC interrupt event | On-chip contents are fully preserved. Any SoC interrupt event can cause a wakeup event from this low power mode. A53 and MCU M4F are in WFI or power down. DDR memory is in self-refresh. The device can run low-level processing with non-Wakeup/MCU domain peripherals and support wakeup from thos peripherals. |
Partial I/O: I/O pins and small logic in the CANUART I/O Bank are active, and the rest of the SoC is turned off. The user can use the I/O pins to aggregate multiple I/O wakeup events and toggle the PMIC_LPM_EN pin to enable PMIC or discrete power solution when an I/O wakeup event is triggered. The information on the I/O wakeup event is logged in the MMR in the CANUART I/O bank and helps the software to distinguish between cold boot and wakeup to respond to the wakeup event faster. This mode can be used to support CAN wakeup or Ethernet Wakeup.
DeepSleep: DeepSleep mode enables lower power consumption than Standby or MCU-Only. DeepSleep mode is typically used during inactivity when the user requires very low power while waiting for an event that requires processing or higher performance. DeepSleep is the lowest power mode which still includes DDR in self-refresh, so wakeup events do not require a full cold boot, significantly reducing wakeup latencies. The lowest power in this mode can be achieved by disabling both oscillators when the RTC or other timer function is not required.
MCU Only: MCU-Only can be used for low power use cases that require low-level processing during a low power mode. The status of the SoC is the same as DeepSleep, except the MCU channel is fully active to run applications with MCU channel resources and peripherals. Any interrupt event in the MCU channel can initiate a wakeup from MCU-Only, and the wakeup events supported in DeepSleep can also trigger wakeup from MCU-Only.
Standby:The device can be placed in Standby mode to reduce power consumption during low activity levels. This first level of power management allows you to maintain the device context for fast resume times. Standby state results in lower power consumption than Active mode but require the user to save the switched-off power domain context to On-Chip Memory or DDR and restore the contexts to resume properly upon wakeup.