The AM62x (AMC) is an extension of the low-power, low-cost Sitara Industrial/Auto grade family of processors. The AM62x (AMC) is based on the Cortex-A53 microprocessor, M4F microcontroller with dedicated peripherals, 3D graphics acceleration, dual display interfaces, and extensive peripheral and networking options for a variety of embedded applications. The AM62x (AMC) is available in a 17.2-mm × 17.2-mm FBGA package with a 0.8-mm ball pitch. The package BGA design is built leveraging TI Flip Chip BGA Technology (FC-BGA) technology. This document is intended to provide a reference for escape routing on the AM62x (AMC) device. Care must be taken to route signals with special requirements such as DDR and high speed interfaces. Refer to the High-Speed Interface Layout Guidelines and DDR Routing Guidelines for more details. Details on Power Delivery Network are provided in AM62x PDN Application note and any routing and layout requirements specified in those documents supersede the generic requirements provided here.

The AM62x (AMC) solution has been designed to support the following. AM62x (AMC) package supports similar feature set as several other competition solutions with approximately 15% smaller package area and ~10% wider line width. This solution reduces PCB foot print and utilizes lower cost PCB rules, enabling compact and low-cost systems.

PCB stack-up is one of the first and important considerations in realizing a successful PCB. The AM62x (AMC) device supports a BGA array or 21 × 21 with a 0.8-mm pitch and a body size of 17.2 mm. Due to the number of rows of signal balls around the periphery, TI recommends two signal routing layers. PDN compliance and robustness is critical to meet all the performance objectives of the device and associated peripherals. To enable this, TI recommends allocating two layers for power planes. Ground planes must be added adjacent to the power planes and adjacent to the outer layers for shielding and controlled impedance routing. High speed interfaces such as DDR, CSI, and USB require ground planes for impedance matching. Additionally, to meet the higher DDR interface speeds, ground layers both above and below the DDR signals are recommended. The escapes and routing on the AM62x (AMC) board design was achieved with 8 layers, as shown in Table 3-1.

An example 8-layer board stack-up for AM62x (AMC) is described above. This board is designed for optimum signal integrity on the high-speed interfaces while limiting the board size. The AM62x (AMC) board is implemented without HDI (High Density Interconnect) and does not use micro vias, which are both intended to save board cost. All vias on the AM62x (AMC) board are Plated Through Hole (PTH) and pass completely through the board. Proper analysis are performed to validate both signal and power integrity, if further optimizations are required to reduce PCB stack-up and/or routing rules illustrated in this document.