SPRUJ53B April 2024 – September 2024 TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SJ-Q1
This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data sheet, rather a companion guide that can be used alongside the device-specific data sheet to understand the details to program the device. The primary purpose of the TRM is to abstract the programming details of the device from the data sheet. This allows the data sheet to outline the high-level features of the device without unnecessary information about register descriptions or programming models.
This document uses the following conventions.
For a complete listing of related documentation and development-support tools for these devices, visit the Texas Instruments website at www.ti.com.
Additionally, the TMS320C28x DSP CPU and Instruction Set Reference Guide and the TMS320C28x Floating Point Unit and Instruction Set Reference Guide must be used in conjunction with this TRM.
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This chapter discusses the C2000Ware for the C2000™ microcontrollers. The C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE
C2000Ware for the C2000™ microcontrollers is a cohesive set of development software and documentation designed to minimize software development time. From device-specific drivers and libraries to device peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE
The C2000Ware software package is organized into the following directory structure as shown in Table 1-1.
Directory Name | Description |
---|---|
boards | Contains the hardware design schematics, BOM, Gerber files, and documentation for C2000 controlCARDS. |
device_support | Contains all device-specific support files, bit field headers and device development user's guides. |
docs | Contains the C2000Ware package user's guides and the HTML index page of all package documentation. |
driverlib | Contains the device-specific driver library and driver-based peripheral examples. |
libraries | Contains the device-specific and core libraries. |
Within C2000Ware, there is an extensive amount of development documentation ranging from board design documentation, to library user's guides, to driver API documentation. The "boards" directory contains all the hardware design, BOM, Gerber files, and more for controlCARDs. To assist with locating the necessary documentation, an HTML page is provided that contains a full list of all the documents in the C2000Ware package. Locate this page in the "docs" directory.
C2000Ware contains the necessary software and documentation to jumpstart development for C2000™ microcontrollers. Each device includes device-specific common source files, peripheral example projects, bit field headers, and if available, a device peripheral driver library. Additionally, documentation is provided for each device on how to set up a CCS project, as well as give an overview of all the included example projects and assist with troubleshooting. For devices with a driver library, documentation is also included that details all the peripheral APIs available.
To learn more about C2000™ microcontrollers, visit: www.ti.com/c2000.
The libraries included in C2000Ware range from fixed-point and floating-point math libraries, to specialized DSP libraries, as well as calibration libraries. Each library includes documentation and examples, where applicable. Additionally, the Flash API files and boot ROM source code are located in the "libraries" directory.
Code Composer Studio™ is an integrated development environment (IDE) that supports TI's microcontroller and embedded processors portfolio. The Code Composer Studio™ IDE comprises a suite of tools used to develop and debug embedded applications. The latest version of Code Composer Studio™ IDE can be obtained at: www.ti.com/ccstudio
All projects and examples in C2000Ware are built for and tested with the Code Composer Studio™ IDE. Although the Code Composer Studio™ IDE is not included with the C2000Ware installer, Code Composer Studio™ IDE is easily obtainable in a variety of versions.
To help simplify configuration challenges and accelerate software development, Texas Instruments™ created SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring pins, peripherals, subsystems, and other components. SysConfig helps you manage, expose, and resolve conflicts visually so that you have more time to create differentiated applications.
The tool's output includes C header and code files that can be used with C2000Ware examples or used to configure custom software.
The SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The SysConfig tool is delivered integrated in the Code Composer Studio™ IDE, in the C2000Ware GPIO example, as a standalone installer, or can be used by way of the cloud tools portal at: dev.ti.com
This chapter contains a short description of the C28x processor and extended instruction sets.
Further information can be found in the following documents:
The C28x CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing, reduced instruction set computing (RISC), microcontroller architectures, firmware, and tool sets.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set Reference Guide.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be performed in parallel. The CPU can read instructions and data while the CPU writes data simultaneously to maintain the single-cycle instruction operation across the pipeline.
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit registers. The additional floating-point unit registers are the following:
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 2-1.
Instructions | C Equivalent Operation | Pipeline Cycles |
---|---|---|
MPY2PIF32 RaH,RbH | a = b * 2pi | 2/3 |
DIV2PIF32 RaH,RbH | a = b / 2pi | 2/3 |
DIVF32 RaH,RbH,RcH | a = b/c | 5 |
SQRTF32 RaH,RbH | a = sqrt(b) | 5 |
SINPUF32 RaH,RbH | a = sin(b*2pi) | 4 |
COSPUF32 RaH,RbH | a = cos(b*2pi) | 4 |
ATANPUF32 RaH,RbH | a = atan(b)/2pi | 4 |
QUADF32 RaH,RbH,RcH,RdH | Operation to assist in calculating ATANPU2 | 5 |
Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computation of floating-point power function for the nonlinear proportional integral derivative control (NLPID) component of the C2000 Digital Control Library. These two added instructions reduce the power function calculations from a typical of 300 cycles using library emulation to less than 10 cycles.
No changes have been made to existing instructions, pipeline, or memory bus architecture. All TMU instructions use the existing FPU register set (R0H to R7H) to carry out the operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit, and 32-bit CRCs. A CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of VCRC:
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16, CRC24 and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC requirements. The CRC execution time increases to 3 cycles when using a custom polynomial.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
The system-level functionality of this microcontroller configures the clocking, resets, and interrupts of the CPU and peripherals, as well as the operation of the on-chip memories, timers, and security features.
System-level configuration is controlled by a group of submodules that are collectively referred to as the system control module. The system control module provides the following capabilities:
Several system configuration registers are protected from spurious CPU writes by LOCK registers. Once these associated LOCK register bits are set, the respective locked registers can no longer be modified by software. See the register descriptions for details.
Some registers in the system are protected from spurious CPU writes by the EALLOW protection mechanism. This uses the special CPU instructions EALLOW and EDIS to enable and disable access to protected registers. The current protection state is given by the EALLOW bit in the CPU ST1 register, as shown in Table 3-1.
Register protection is enabled by default at startup. While protected, all writes to protected registers by the CPU are ignored. Only CPU reads, JTAG reads, and JTAG writes are allowed. If protection is disabled by executing the EALLOW instruction, the CPU is allowed to write freely to protected registers. After modifying registers, the registers can once again be protected by executing the EDIS instruction to clear the EALLOW bit.
Writes to the clock configuration and peripheral clock enable registers can be disabled until the next reset by writing to special lock registers.
EALLOW Bit | CPU Writes | CPU Reads | JTAG Writes | JTAG Reads |
---|---|---|---|---|
0 | Ignored | Allowed(1) | Allowed | Allowed |
1 | Allowed | Allowed | Allowed | Allowed |
The TMS320F28P55x MCU supports both internal generation of the 1.2V rail for single-supply operation or externally supplied 1.2V into the device. The internal VREG is controlled using the VREGENZ pin: if enabled, the 1.2V rail is generated by the device; if disabled, the 1.2V rail is supplied from an external source. For more details, see TMS320F28P55x Real-Time Microcontrollers.
The device identification registers and configuration registers provide information on the part number, product family, revision, pin count, qualification status, and feature availability of the device.
All of the device information is part of the DEV_CFG_REGS space. The identification registers are PARTIDL, PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
This section explains the types and effects of the different resets on this device.
Table 3-2 summarizes the various reset signals and the effect on the device.
Reset Source | CPU Core Reset (C28x, FPU, VCU) |
Peripherals Reset |
JTAG / Debug Logic Reset | IOs | XRS Output |
---|---|---|---|---|---|
POR | Yes | Yes | Yes | Hi-Z | Yes |
BOR | Yes | Yes | Yes | Hi-Z | Yes |
XRS Pin | Yes | Yes | No | Hi-Z | - |
WDRS | Yes | Yes | No | Hi-Z | Yes |
NMIWDRS | Yes | Yes | No | Hi-Z | Yes |
SYSRS (Debugger Reset) | Yes | Yes | No | Hi-Z | No |
SCCRESET | Yes | Yes | No | Hi-Z | No |
SIMRESET.XRS | Yes | Yes | No | Hi-Z | Yes |
SIMRESET.CPU1RS | Yes | Yes | No | Hi-Z | No |
The resets can be divided into two groups:
After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register maintain the state across multiple resets. The bits can only be cleared by a power-on reset (POR) or by writing ones to the RESCCLR register. Some are cleared by the boot ROM as part of the start-up routines.
Many peripheral modules have individual resets accessible through the SOFTPRESx registers. For information about a module's reset state, refer to the appropriate chapter for that module.
After any reset, the CPU begins execution from address 0x3FFFC0 (the reset vector), which is in the boot ROM. After running the boot ROM code, the CPU typically branches to the start of the Flash memory at address 0x80000. For more information on controlling the boot process, see Chapter 4 .
The external reset (XRS) is the main chip-level reset for the device and resets the CPU, all peripherals and I/O pin configurations, and most of the system control registers. There is a dedicated open-drain pin for XRS. This pin can be used to drive reset pins for other ICs in the application, and can be driven by an external source. The XRS is driven internally during watchdog, NMI, and power-on resets.
The XRSn bit in the RESC register is set whenever XRS is driven low for any reason. This bit is then cleared by the boot ROM.
In some cases, the user can need to simulate the external reset (XRS) in software. This can be done using software by setting XRSn bit to 1 in SIMRESET register. This toggles the XRS pin and resets the full device (just like an external reset).
After this reset, the SIMRESET_XRSn and XRSn bits in the RESC register are set. Software can read these bits to know the cause of reset and clear the status by writing a 1 into corresponding bits in RESCCLR register.
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up, suppressing glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most applications, XRS is held low long enough to reset other system ICs, but some applications can require a longer pulse. In these cases, the XRS pin can be driven low externally to provide the correct reset duration. A POR resets everything that XRS does, along with a few other registers – the reset cause register (RESC), the NMI shadow flag register (NMISHDFLG), and the X1 clock counter register (X1CNT). A POR also resets the debug logic used by the JTAG port.
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.
The brown-out reset (BOR) is an internal supply voltage supervisor (SVS) circuit that monitors the VDDIO supply for glitches or supply interruptions. If the VDDIO supply voltage drops below operational voltage range, this circuit forces the XRSn pin low until the fault is removed and the supply voltage returns to the minimum operational voltage. A BOR resets everything in the same manner as a POR reset.
The BOR circuit is enabled by default and is always active during power up or after any type of reset. To disable the BOR circuit, set the BORLVMONDIS bit in the VMONCTL register.
During development, it is sometimes necessary to reset the CPU and the peripherals without disconnecting the debugger or disrupting the system-level configuration. To facilitate this, the CPU has a subsystem reset, which can be triggered by a debugger using Code Composer Studio™ IDE. This reset (SYSRS) resets the CPU, the peripherals, many system control registers (including the clock gating and LPM configuration), and all I/O pin configurations.
The SYSRS does not reset the ICEPick debug module, the device capability registers, the clock source and PLL configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI flags, the analog trims, or anything reset only by a POR (see Section 3.4.4).
In some cases, you can simulate the CPU reset (SYSRS) in software. This can be done by setting the CPU1RSn bit to 1 in the SIMRESET register by CPU1 software. This toggles CPU1.SYSRS signals, resetting the CPU (just like the debugger reset).
After this reset, the SIMRESET_CPU1RSn bit in the RESC register is set. Software can read this bit to know the cause of the reset and clear the status by writing a 1 into the corresponding bit in the RESCCLR register.
The device has a watchdog timer that can optionally trigger a reset if it is not serviced by the CPU within a user-specified amount of time. This watchdog reset (WDRS) produces an XRS that lasts for 512 INTOSC1 cycles.
After a watchdog reset, the WDRSn and XRSn bits in RESC are set.
The device has a non-maskable interrupt (NMI) module that detects hardware errors in the system. The NMI module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a user-specified amount of time. This NMI watchdog reset (NMIWDRS) produces an XRS that lasts for 512 INTOSC1 cycles.
After an NMI watchdog reset, the NMIWDRSn and XRSn bits in RESC are set.
The device has a dual-zone code security module (DCSM) that blocks read access to certain areas of the Flash memory. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely access those memory areas. To prevent security breaches, interrupts must be disabled before calling these functions. If a vector fetch occurs in a safe copy or CRC function, the DCSM triggers a reset. This security reset (SCCRESET) is similar to a SYSRS. However, the security reset also resets the debug logic to deny access to a potential attacker.
After a security reset, the SCCRESETn bit in RESC is set.
This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered in Section 3.6. Software interrupts and emulation interrupts are not covered in this chapter (see the TMS320C28x CPU and Instruction Set Reference Guide).
An interrupt is a signal that causes the CPU to pause the current execution and branch to a different piece of code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral events, and involves less CPU overhead or program complexity than register polling. However, because interrupts are asynchronous to the program flow, care must be taken to avoid conflicts over resources that are accessed both in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the interrupt until the interrupt is processed. The enable registers block the propagation of the interrupt. When an interrupt signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the vector table.
The C28x CPU has 14 peripheral interrupt lines. Two of the interrupts (INT13 and INT14) are connected directly to CPU timers 1 and 2, respectively. The remaining 12 interrupts are connected to peripheral interrupt signals through the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened version). The PIE multiplexes up to 16 peripheral interrupts into each CPU interrupt line and also expands the vector table to allow each interrupt to have an ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages: the peripheral, the PIE, and the CPU. Each stage has enable and flag registers. This system allows the CPU to handle one interrupt while others are pending, implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 3-1 shows the interrupt architecture for this device.
Each peripheral has a unique interrupt configuration, which is described in that peripheral's chapter. Some peripherals allow multiple events to trigger the same interrupt signal. For example, a communications peripheral can use the same interrupt to indicate that data has been received or that there has been a transmission error. The cause of the interrupt can be determined by reading the peripheral's status register. Often, the bits in the status register must be cleared manually before another interrupt is generated.
The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which are sometimes called PIE channels. These channels are grouped according to the associated CPU interrupt. Each PIE group has one 8-bit enable register (PIEIERx), one 8-bit flag register (PIEIFRx) , and one bit in the PIE acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt mask for the entire PIE group.
When the CPU receives an interrupt, the CPU fetches the address of the ISR from the PIE. The PIE returns the vector for the lowest-numbered channel in the group that is both flagged and enabled. This gives lower-numbered interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition does not happen unless software changes the state of the PIE while an interrupt is propagating. Section 3.5.4 contains procedures for safely modifying the PIE configuration once interrupts have been enabled.
Like the PIE, the CPU provides flag and enable register bits for each of the interrupts. There is one enable register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared using the CPU's SETC and CLRC instructions. In C code, C2000Ware's DINT and EINT macros can be used for this purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is set, the next instruction in the pipeline runs with interrupts disabled. No software delays are needed.
Figure 3-2 shows how peripheral interrupts propagate to the CPU.
When a peripheral generates an interrupt (on PIE group x, channel y), the interrupt triggers the following sequence of events:
The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction entering the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles. Wait states on the ISR or stack memories add to the latency. External interrupts add a minimum of two SYSCLK cycles for GPIO synchronization plus extra time for input qualification (if used). Loops created using the C28x RPT instruction cannot be interrupted.
At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is set. The application code is responsible for configuring and enabling all peripheral interrupts.
To enable a peripheral interrupt, perform the following steps:
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
ISRs are similar to normal functions, but must do the following:
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined using the __interrupt keyword. For information on this keyword, see the Keywords section of the TMS320C28x Optimizing C/C++ Compiler v6.2.4 User's Guide. For information on writing assembly code to handle interrupts, see the Standard Operation for Maskable Interrupts section of the TMS320C28x CPU and Instruction Set Reference Guide.
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at the end of the ISR. If the PIEACK bit is not cleared, the CPU does not receive any further interrupts from that group. This does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.
To disable all interrupts, set the CPUs global interrupt mask using DINT or SETC INTM. It is not necessary to add NOPs after setting INTM or modifying IER – the next instruction executes with interrupts disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race conditions. If an interrupt signal is already propagating when the PIEIER write completes, the interrupt signal can reach the CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no special procedure is needed.
The PIEIFR bits must never be cleared in software since the read/modify/write operation can cause incoming interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The following procedure can be used to bypass the normal ISR:
By default, interrupts do not nest. It is possible to nest and prioritize interrupts using software control of the IER and PIEIERx registers. Example code can be found in C2000Ware and documentation is available at software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html.
The ePIE vector table memory is protected using a parity check. Upon each vector fetch from the ePIE, a parity check is performed. If a parity failure occurs during vector fetch, the ePIE returns either a user defined error handler routine (if PIEVERRADDR is defined with a non 0x003FFFFF value), or the default boot ROM handler at address 0x3FFFBE. The ePIE also sends trip signals to the EPWMs.
The parity check only returns the error handler value if the failure occurs during vector fetch. Parity errors during data read is handled by the memory controller module and logged by UCERRFLG register in MEMORY_ERROR_REGS. The address that caused the error is located in the UCCPUREADDR register. If the error address logged is between 0xD00 to 0xDFF, then the error is a PIE parity error. Additionally, a parity error during vector fetch does not flag an uncorrectable error NMI.
Table 3-3 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within that group. When multiple interrupts are pending, the lowest-numbered channel is the lowest-numbered group is serviced first. Thus, the interrupts at the top of the table have the highest priority, and the interrupts at the bottom have the lowest priority.
INTx.1 | INTx.2 | INTx.3 | INTx.4 | INTx.5 | INTx.6 | INTx.7 | INTx.8 | INTx.9 | INTx.10 | INTx.11 | INTx.12 | INTx.13 | INTx.14 | INTx.15 | INTx.16 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INT1.y | ADCA1 | ADCB1 | ADCC1 | XINT1 | XINT2 | SYS_ERR | TIMER0 | WAKE | ADCD1 | ADCE1 | ||||||
INT2.y | EPWM1_TZ | EPWM2_TZ | EPWM3_TZ | EPWM4_TZ | EPWM5_TZ | EPWM6_TZ | EPWM7_TZ | EPWM8_TZ | EPWM9_TZ | EPWM10_TZ | EPWM11_TZ | EPWM12_TZ | ||||
INT3.y | EPWM1 | EPWM2 | EPWM3 | EPWM4 | EPWM5 | EPWM6 | EPWM7 | EPWM8 | EPWM9 | EPWM10 | EPWM11 | EPWM12 | ||||
INT4.y | ECAP1 | ECAP2 | ||||||||||||||
INT5.y | EQEP1 | EQEP2 | EQEP3 | CLB1 | CLB2 | |||||||||||
INT6.y | SPIA_RX | SPIA_TX | SPIB_RX | SPIB_TX | DCC0 | DCC1 | ||||||||||
INT7.y | DMA_CH1 | DMA_CH2 | DMA_CH3 | DMA_CH4 | DMA_CH5 | DMA_CH6 | PMBUSA | FSITXA_INT1 | FSITXA_INT2 | FSIRXA_INT1 | FSIRXA_INT2 | |||||
INT8.y | I2CA | I2CA_FIFO | I2CB | I2CB_FIFO | SCIC_RX | SCIC_TX | LINA_0 | LINA_1 | ||||||||
INT9.y | SCIA_RX | SCIA_TX | SCIB_RX | SCIB_TX | MCANASS0 | MCANASS1 | MCANBSS0 | MCANBSS1 | MCANBSS_ECC_CORR_PLS | MCANBSS_WAKE_AND_TS_PLS | USB | NPU | ||||
INT10.y | ADCA_EVT | ADCA2 | ADCA3 | ADCA4 | ADCB_EVT | ADCB2 | ADCB3 | ADCB4 | ADCC_EVT | ADCC2 | ADCC3 | ADCC4 | ADCD_EVT | ADCD2 | ADCD3 | ADCD4 |
INT11.y | CLA1_1 | CLA1_2 | CLA1_3 | CLA1_4 | CLA1_5 | CLA1_6 | CLA1_7 | CLA1_8 | ADCE_EVT | ADCE2 | ADCE3 | ADCE4 | ||||
INT12.y | XINT3 | XINT4 | XINT5 | FLSS_INT | MCANASS_WAKE_AND_TS_PLS | MCANASS_ECC_CORR_PLS | AES_INT |
For every PIE group, the low number channels in the group have the highest priority. For instance in PIE group 1, channel 1.1 has priority over channel 1.3. If those two enabled interrupts occurred simultaneously, channel 1.1 is serviced first with channel 1.3 left pending. Once the ISR for channel 1.1 completes and provided there are no other enabled and pending interrupts for PIE group 1, channel 1.3 is serviced. However, for the CPU to service any more interrupts from a PIE group, PIEACK for the group must be cleared. For this specific example, for channel 1.3 to be serviced, channel 1.1’s ISR has to clear PIEACK for group 1.
The following example describes an alternative scenario: channel 1.1 is currently being serviced by the CPU, channel 1.3 is pending and before channel 1.1’s ISR completes, channel 1.2 that is enabled also comes in. Since channel 1.2 has a higher priority than channel 1.3, the CPU services channel 1.2 and channel 1.3 is still left pending. Using the steps from the Interrupt Entry Sequence (Section 3.5.3), channel 1.2 interrupt can happen as late as step 10 (the CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared) and the channel is still serviced ahead of channel 1.3.
Generally, the lowest channel in the lowest PIE group has the highest priority. An example of this is channels 1.1 and 2.1. Those two channels have the highest priority in the respective groups. If the interrupts for those two enabled channels happened simultaneously and provided there are no other enabled and pending interrupts, channel 1.1 is serviced first by the CPU with channel 2.1 left pending.
However, there are cases where channel priority supersedes group priority. This special case happens depending on which step the CPU is currently at in the Interrupt Entry Sequence (Section 3.5.3).
The following illustrates an example of this special case.
The CPU is about to service channel 2.3 and is currently going through the steps in the Interrupt Entry Sequence (Section 3.5.3).
Group priority is only specified if no interrupts are currently being serviced, that is, the Interrupt Entry Sequence (Section 3.5.3) is not executing.
SYS_ERR consolidate several sources of interrupts (see Figure 3-3). These sources set the respective bit in the SYS_ERR_INT_FLG register. Any set bit in the SYS_ERR_INT_FLG register also sets the global interrupt (GINT) bit. The GINT bit has to be cleared before any SYS_ERR interrupt is generated. If the GINT bit is cleared with the source flags still set, another SYS_ERR interrupt is fired; therefore, it is recommended to clear the source flags before clearing the GINT bit.
Table 3-4 shows the CPU interrupt vector table. The vectors for INT1–INT12 are not used in this device. The reset vector is fetched from the boot ROM instead of from this table. All vectors are EALLOW-protected.
Table 3-5 shows the PIE vector table.
Name | Vector ID | Address | Size (x16) | Description | Core Priority | ePIE Group Priority |
---|---|---|---|---|---|---|
Reset | 0 | 0x0000 0D00 | 2 | Reset is always fetched from location 0x003F_FFC0 in Boot ROM | 1 (Highest) | - |
INT1 | 1 | 0x0000 0D02 | 2 | Not used. See PIE Group 1 | 5 | - |
INT2 | 2 | 0x0000 0D04 | 2 | Not used. See PIE Group 2 | 6 | - |
INT3 | 3 | 0x0000 0D06 | 2 | Not used. See PIE Group 3 | 7 | - |
INT4 | 4 | 0x0000 0D08 | 2 | Not used. See PIE Group 4 | 8 | - |
INT5 | 5 | 0x0000 0D0A | 2 | Not used. See PIE Group 5 | 9 | - |
INT6 | 6 | 0x0000 0D0C | 2 | Not used. See PIE Group 6 | 10 | - |
INT7 | 7 | 0x0000 0D0E | 2 | Not used. See PIE Group 7 | 11 | - |
INT8 | 8 | 0x0000 0D10 | 2 | Not used. See PIE Group 8 | 12 | - |
INT9 | 9 | 0x0000 0D12 | 2 | Not used. See PIE Group 9 | 13 | - |
INT10 | 10 | 0x0000 0D14 | 2 | Not used. See PIE Group 10 | 14 | - |
INT11 | 11 | 0x0000 0D16 | 2 | Not used. See PIE Group 11 | 15 | - |
INT12 | 12 | 0x0000 0D18 | 2 | Not used. See PIE Group 12 | 16 | - |
INT13 | 13 | 0x0000 0D1A | 2 | CPU TIMER1 Interrupt | 17 | - |
INT14 | 14 | 0x0000 0D1C | 2 | CPU TIMER2 Interrupt | 18 | - |
DATALOG | 15 | 0x0000 0D1E | 2 | CPU Data Logging Interrupt | 19 (lowest) | - |
RTOSINT | 16 | 0x0000 0D20 | 2 | CPU Real-Time OS Interrupt | 4 | - |
RSVD | 17 | 0x0000 0D22 | 2 | Reserved | 2 | - |
NMI | 18 | 0x0000 0D24 | 2 | Non-Maskable Interrupt | 3 | - |
ILLEGAL | 19 | 0x0000 0D26 | 2 | Illegal Instruction (ITRAP) | - | - |
USER 1 | 20 | 0x0000 0D28 | 2 | User-Defined Trap | - | - |
USER 2 | 21 | 0x0000 0D2A | 2 | User-Defined Trap | - | - |
USER 3 | 22 | 0x0000 0D2C | 2 | User-Defined Trap | - | - |
USER 4 | 23 | 0x0000 0D2E | 2 | User-Defined Trap | - | - |
USER 5 | 24 | 0x0000 0D30 | 2 | User-Defined Trap | - | - |
USER 6 | 25 | 0x0000 0D32 | 2 | User-Defined Trap | - | - |
USER 7 | 26 | 0x0000 0D34 | 2 | User-Defined Trap | - | - |
USER 8 | 27 | 0x0000 0D36 | 2 | User-Defined Trap | - | - |
USER 9 | 28 | 0x0000 0D38 | 2 | User-Defined Trap | - | - |
USER 10 | 29 | 0x0000 0D3A | 2 | User-Defined Trap | - | - |
USER 11 | 30 | 0x0000 0D3C | 2 | User-Defined Trap | - | - |
USER 12 | 31 | 0x0000 0D3E | 2 | User-Defined Trap | - | - |
Name | Vector ID | Address | Size (x16) | Description | Core Priority | ePIE Group priority |
---|---|---|---|---|---|---|
PIE Group 1 Vectors - Muxed into CPU INT1 | ||||||
INT1.1 | 32 | 0x0000 0D40 | 2 | ADCA1 interrupt | 5 | 1 (Highest) |
INT1.2 | 33 | 0x0000 0D42 | 2 | ADCB1 interrupt | 5 | 2 |
INT1.3 | 34 | 0x0000 0D44 | 2 | ADCC1 interrupt | 5 | 3 |
INT1.4 | 35 | 0x0000 0D46 | 2 | XINT1 interrupt | 5 | 4 |
INT1.5 | 36 | 0x0000 0D48 | 2 | XINT2 interrupt | 5 | 5 |
INT1.6 | 37 | 0x0000 0D4A | 2 | SYS_ERR interrupt | 5 | 6 |
INT1.7 | 38 | 0x0000 0D4C | 2 | TIMER0 interrupt | 5 | 7 |
INT1.8 | 39 | 0x0000 0D4E | 2 | WAKE interrupt | 5 | 8 |
INT1.9 | 128 | 0x0000 0E00 | 2 | ADCD1 interrupt | 5 | 9 |
INT1.10 | 129 | 0x0000 0E02 | 2 | ADCE1 interrupt | 5 | 10 |
INT1.11 | 130 | 0x0000 0E04 | 2 | Reserved | 5 | 11 |
INT1.12 | 131 | 0x0000 0E06 | 2 | Reserved | 5 | 12 |
INT1.13 | 132 | 0x0000 0E08 | 2 | Reserved | 5 | 13 |
INT1.14 | 133 | 0x0000 0E0A | 2 | Reserved | 5 | 14 |
INT1.15 | 134 | 0x0000 0E0C | 2 | Reserved | 5 | 15 |
INT1.16 | 135 | 0x0000 0E0E | 2 | Reserved | 5 | 16 (Lowest) |
PIE Group 2 Vectors - Muxed into CPU INT2 | ||||||
INT2.1 | 40 | 0x0000 0D50 | 2 | EPWM1 trip zone interrupt | 6 | 1 (Highest) |
INT2.2 | 41 | 0x0000 0D52 | 2 | EPWM2 trip zone interrupt | 6 | 2 |
INT2.3 | 42 | 0x0000 0D54 | 2 | EPWM3 trip zone interrupt | 6 | 3 |
INT2.4 | 43 | 0x0000 0D56 | 2 | EPWM4 trip zone interrupt | 6 | 4 |
INT2.5 | 44 | 0x0000 0D58 | 2 | EPWM5 trip zone interrupt | 6 | 5 |
INT2.6 | 45 | 0x0000 0D5A | 2 | EPWM6 trip zone interrupt | 6 | 6 |
INT2.7 | 46 | 0x0000 0D5C | 2 | EPWM7 trip zone interrupt | 6 | 7 |
INT2.8 | 47 | 0x0000 0D5E | 2 | EPWM8 trip zone interrupt | 6 | 8 |
INT2.9 | 136 | 0x0000 0E10 | 2 | EPWM9 trip zone interrupt | 6 | 9 |
INT2.10 | 137 | 0x0000 0E12 | 2 | EPWM10 trip zone interrupt | 6 | 10 |
INT2.11 | 138 | 0x0000 0E14 | 2 | EPWM11 trip zone interrupt | 6 | 11 |
INT2.12 | 139 | 0x0000 0E16 | 2 | EPWM12 trip zone interrupt | 6 | 12 |
INT2.13 | 140 | 0x0000 0E18 | 2 | Reserved | 6 | 13 |
INT2.14 | 141 | 0x0000 0E1A | 2 | Reserved | 6 | 14 |
INT2.15 | 142 | 0x0000 0E1C | 2 | Reserved | 6 | 15 |
INT2.16 | 143 | 0x0000 0E1E | 2 | Reserved | 6 | 16 (Lowest) |
PIE Group 3 Vectors - Muxed into CPU INT3 | ||||||
INT3.1 | 48 | 0x0000 0D60 | 2 | EPWM1 interrupt | 7 | 1 (Highest) |
INT3.2 | 49 | 0x0000 0D62 | 2 | EPWM2 interrupt | 7 | 2 |
INT3.3 | 50 | 0x0000 0D64 | 2 | EPWM3 interrupt | 7 | 3 |
INT3.4 | 51 | 0x0000 0D66 | 2 | EPWM4 interrupt | 7 | 4 |
INT3.5 | 52 | 0x0000 0D68 | 2 | EPWM5 interrupt | 7 | 5 |
INT3.6 | 53 | 0x0000 0D6A | 2 | EPWM6 interrupt | 7 | 6 |
INT3.7 | 54 | 0x0000 0D6C | 2 | EPWM7 interrupt | 7 | 7 |
INT3.8 | 55 | 0x0000 0D6E | 2 | EPWM8 interrupt | 7 | 8 |
INT3.9 | 144 | 0x0000 0E20 | 2 | EPWM9 interrupt | 7 | 9 |
INT3.10 | 145 | 0x0000 0E22 | 2 | EPWM10 interrupt | 7 | 10 |
INT3.11 | 146 | 0x0000 0E24 | 2 | EPWM11 interrupt | 7 | 11 |
INT3.12 | 147 | 0x0000 0E26 | 2 | EPWM12 interrupt | 7 | 12 |
INT3.13 | 148 | 0x0000 0E28 | 2 | Reserved | 7 | 13 |
INT3.14 | 149 | 0x0000 0E2A | 2 | Reserved | 7 | 14 |
INT3.15 | 150 | 0x0000 0E2C | 2 | Reserved | 7 | 15 |
INT3.16 | 151 | 0x0000 0E2E | 2 | Reserved | 7 | 16 (Lowest) |
PIE Group 4 Vectors - Muxed into CPU INT4 | ||||||
INT4.1 | 56 | 0x0000 0D70 | 2 | ECAP1 interrupt | 8 | 1 (Highest) |
INT4.2 | 57 | 0x0000 0D72 | 2 | ECAP2 interrupt | 8 | 2 |
INT4.3 | 58 | 0x0000 0D74 | 2 | Reserved | 8 | 3 |
INT4.4 | 59 | 0x0000 0D76 | 2 | Reserved | 8 | 4 |
INT4.5 | 60 | 0x0000 0D78 | 2 | Reserved | 8 | 5 |
INT4.6 | 61 | 0x0000 0D7A | 2 | Reserved | 8 | 6 |
INT4.7 | 62 | 0x0000 0D7C | 2 | Reserved | 8 | 7 |
INT4.8 | 63 | 0x0000 0D7E | 2 | Reserved | 8 | 8 |
INT4.9 | 152 | 0x0000 0E30 | 2 | Reserved | 8 | 9 |
INT4.10 | 153 | 0x0000 0E32 | 2 | Reserved | 8 | 10 |
INT4.11 | 154 | 0x0000 0E34 | 2 | Reserved | 8 | 11 |
INT4.12 | 155 | 0x0000 0E36 | 2 | Reserved | 8 | 12 |
INT4.13 | 156 | 0x0000 0E38 | 2 | Reserved | 8 | 13 |
INT4.14 | 157 | 0x0000 0E3A | 2 | Reserved | 8 | 14 |
INT4.15 | 158 | 0x0000 0E3C | 2 | Reserved | 8 | 15 |
INT4.16 | 159 | 0x0000 0E3E | 2 | Reserved | 8 | 16 (Lowest) |
PIE Group 5 Vectors - Muxed into CPU INT5 | ||||||
INT5.1 | 64 | 0x0000 0D80 | 2 | EQEP1 interrupt | 9 | 1 (Highest) |
INT5.2 | 65 | 0x0000 0D82 | 2 | EQEP2 interrupt | 9 | 2 |
INT5.3 | 66 | 0x0000 0D84 | 2 | EQEP3 interrupt | 9 | 3 |
INT5.4 | 67 | 0x0000 0D86 | 2 | Reserved | 9 | 4 |
INT5.5 | 68 | 0x0000 0D88 | 2 | CLB1 interrupt | 9 | 5 |
INT5.6 | 69 | 0x0000 0D8A | 2 | CLB2 interrupt | 9 | 6 |
INT5.7 | 70 | 0x0000 0D8C | 2 | Reserved | 9 | 7 |
INT5.8 | 71 | 0x0000 0D8E | 2 | Reserved | 9 | 8 |
INT5.9 | 160 | 0x0000 0E40 | 2 | Reserved | 9 | 9 |
INT5.10 | 161 | 0x0000 0E42 | 2 | Reserved | 9 | 10 |
INT5.11 | 162 | 0x0000 0E44 | 2 | Reserved | 9 | 11 |
INT5.12 | 163 | 0x0000 0E46 | 2 | Reserved | 9 | 12 |
INT5.13 | 164 | 0x0000 0E48 | 2 | Reserved | 9 | 13 |
INT5.14 | 165 | 0x0000 0E4A | 2 | Reserved | 9 | 14 |
INT5.15 | 166 | 0x0000 0E4C | 2 | Reserved | 9 | 15 |
INT5.16 | 167 | 0x0000 0E4E | 2 | Reserved | 9 | 16 (Lowest) |
PIE Group 6 Vectors - Muxed into CPU INT6 | ||||||
INT6.1 | 72 | 0x0000 0D90 | 2 | SPIA RX interrupt | 10 | 1 (Highest) |
INT6.2 | 73 | 0x0000 0D92 | 2 | SPIA TX interrupt | 10 | 2 |
INT6.3 | 74 | 0x0000 0D94 | 2 | SPIB RX interrupt | 10 | 3 |
INT6.4 | 75 | 0x0000 0D96 | 2 | SPIB TX interrupt | 10 | 4 |
INT6.5 | 76 | 0x0000 0D98 | 2 | Reserved | 10 | 5 |
INT6.6 | 77 | 0x0000 0D9A | 2 | Reserved | 10 | 6 |
INT6.7 | 78 | 0x0000 0D9C | 2 | DCC0 interrupt | 10 | 7 |
INT6.8 | 79 | 0x0000 0D9E | 2 | DCC1 interrupt | 10 | 8 |
INT6.9 | 168 | 0x0000 0E50 | 2 | Reserved | 10 | 9 |
INT6.10 | 169 | 0x0000 0E52 | 2 | Reserved | 10 | 10 |
INT6.11 | 170 | 0x0000 0E54 | 2 | Reserved | 10 | 11 |
INT6.12 | 171 | 0x0000 0E56 | 2 | Reserved | 10 | 12 |
INT6.13 | 172 | 0x0000 0E58 | 2 | Reserved | 10 | 13 |
INT6.14 | 173 | 0x0000 0E5A | 2 | Reserved | 10 | 14 |
INT6.15 | 174 | 0x0000 0E5C | 2 | Reserved | 10 | 15 |
INT6.16 | 175 | 0x0000 0E5E | 2 | Reserved | 10 | 16 (Lowest) |
PIE Group 7 Vectors - Muxed into CPU INT7 | ||||||
INT7.1 | 80 | 0x0000 0DA0 | 2 | DMA CH1 Interrupt | 11 | 1 (Highest) |
INT7.2 | 81 | 0x0000 0DA2 | 2 | DMA CH2 Interrupt | 11 | 2 |
INT7.3 | 82 | 0x0000 0DA4 | 2 | DMA CH3 Interrupt | 11 | 3 |
INT7.4 | 83 | 0x0000 0DA6 | 2 | DMA CH4 Interrupt | 11 | 4 |
INT7.5 | 84 | 0x0000 0DA8 | 2 | DMA CH5 Interrupt | 11 | 5 |
INT7.6 | 85 | 0x0000 0DAA | 2 | DMA CH6 Interrupt | 11 | 6 |
INT7.7 | 86 | 0x0000 0DAC | 2 | PMBUSA | 11 | 7 |
INT7.8 | 87 | 0x0000 0DAE | 2 | Reserved | 11 | 8 |
INT7.9 | 176 | 0x0000 0E60 | 2 | Reserved | 11 | 9 |
INT7.10 | 177 | 0x0000 0E62 | 2 | Reserved | 11 | 10 |
INT7.11 | 178 | 0x0000 0E64 | 2 | FSITX INT1 Interrupt | 11 | 11 |
INT7.12 | 179 | 0x0000 0E66 | 2 | FSITX INT2 Interrupt | 11 | 12 |
INT7.13 | 180 | 0x0000 0E68 | 2 | FSIRX INT1 Interrupt | 11 | 13 |
INT7.14 | 181 | 0x0000 0E6A | 2 | FSIRX INT2 Interrupt | 11 | 14 |
INT7.15 | 182 | 0x0000 0E6C | 2 | Reserved | 11 | 15 |
INT7.16 | 183 | 0x0000 0E6E | 2 | Reserved | 11 | 16 (Lowest) |
PIE Group 8 Vectors - Muxed into CPU INT8 | ||||||
INT8.1 | 88 | 0x0000 0DB0 | 2 | I2CA interrupt | 12 | 1 (Highest) |
INT8.2 | 89 | 0x0000 0DB2 | 2 | I2CA FIFO interrupt | 12 | 2 |
INT8.3 | 90 | 0x0000 0DB4 | 2 | I2CB interrupt | 12 | 3 |
INT8.4 | 91 | 0x0000 0DB6 | 2 | I2CB FIFO interrupt | 12 | 4 |
INT8.5 | 92 | 0x0000 0DB8 | 2 | SCIC RX interrupt | 12 | 5 |
INT8.6 | 93 | 0x0000 0DBA | 2 | SCIC TX interrupt | 12 | 6 |
INT8.7 | 94 | 0x0000 0DBC | 2 | Reserved | 12 | 7 |
INT8.8 | 95 | 0x0000 0DBE | 2 | Reserved | 12 | 8 |
INT8.9 | 184 | 0x0000 0E70 | 2 | LINA INT1 Interrupt | 12 | 9 |
INT8.10 | 185 | 0x0000 0E72 | 2 | LINA INT2 Interrupt | 12 | 10 |
INT8.11 | 186 | 0x0000 0E74 | 2 | Reserved | 12 | 11 |
INT8.12 | 187 | 0x0000 0E76 | 2 | Reserved | 12 | 12 |
INT8.13 | 188 | 0x0000 0E78 | 2 | Reserved | 12 | 13 |
INT8.14 | 189 | 0x0000 0E7A | 2 | Reserved | 12 | 14 |
INT8.15 | 190 | 0x0000 0E7C | 2 | Reserved | 12 | 15 |
INT8.16 | 191 | 0x0000 0E7E | 2 | Reserved | 12 | 16 (Lowest) |
PIE Group 9 Vectors - Muxed into CPU INT9 | ||||||
INT9.1 | 96 | 0x0000 0DC0 | 2 | SCIA RX interrupt | 13 | 1 (Highest) |
INT9.2 | 97 | 0x0000 0DC2 | 2 | SCIA TX interrupt | 13 | 2 |
INT9.3 | 98 | 0x0000 0DC4 | 2 | SCIB RX interrupt | 13 | 3 |
INT9.4 | 99 | 0x0000 0DC6 | 2 | SCIB TX interrupt | 13 | 4 |
INT9.5 | 100 | 0x0000 0DC8 | 2 | Reserved | 13 | 5 |
INT9.6 | 101 | 0x0000 0DCA | 2 | Reserved | 13 | 6 |
INT9.7 | 102 | 0x0000 0DCC | 2 | MCANA INT0 interrupt | 13 | 7 |
INT9.8 | 103 | 0x0000 0DCE | 2 | MCANA INT1 interrupt | 13 | 8 |
INT9.9 | 192 | 0x0000 0E80 | 2 | MCANB INT0 interrupt | 13 | 9 |
INT9.10 | 193 | 0x0000 0E82 | 2 | MCANB INT1 interrupt | 13 | 10 |
INT9.11 | 194 | 0x0000 0E84 | 2 | MCANB ECC interrupt | 13 | 11 |
INT9.12 | 195 | 0x0000 0E86 | 2 | MCANB WAKE interrupt | 13 | 12 |
INT9.13 | 196 | 0x0000 0E88 | 2 | Reserved | 13 | 13 |
INT9.14 | 197 | 0x0000 0E8A | 2 | Reserved | 13 | 14 |
INT9.15 | 198 | 0x0000 0E8C | 2 | USB Interrupt | 13 | 15 |
INT9.16 | 199 | 0x0000 0E8E | 2 | NPU Interrupt | 13 | 16 (Lowest) |
PIE Group 10 Vectors - Muxed into CPU INT10 | ||||||
INT10.1 | 104 | 0x0000 0DD0 | 2 | ADCA event interrupt | 14 | 1 (Highest) |
INT10.2 | 105 | 0x0000 0DD2 | 2 | ADCA2 interrupt | 14 | 2 |
INT10.3 | 106 | 0x0000 0DD4 | 2 | ADCA3 interrupt | 14 | 3 |
INT10.4 | 107 | 0x0000 0DD6 | 2 | ADCA4 interrupt | 14 | 4 |
INT10.5 | 108 | 0x0000 0DD8 | 2 | ADCB event interrupt | 14 | 5 |
INT10.6 | 109 | 0x0000 0DDA | 2 | ADCB2 interrupt | 14 | 6 |
INT10.7 | 110 | 0x0000 0DDC | 2 | ADCB3 interrupt | 14 | 7 |
INT10.8 | 111 | 0x0000 0DDE | 2 | ADCB4 interrupt | 14 | 8 |
INT10.9 | 200 | 0x0000 0E90 | 2 | ADCC event interrupt | 14 | 9 |
INT10.10 | 201 | 0x0000 0E92 | 2 | ADCC2 interrupt | 14 | 10 |
INT10.11 | 202 | 0x0000 0E94 | 2 | ADCC3 interrupt | 14 | 11 |
INT10.12 | 203 | 0x0000 0E96 | 2 | ADCC4 interrupt | 14 | 12 |
INT10.13 | 204 | 0x0000 0E98 | 2 | ADCD event interrupt | 14 | 13 |
INT10.14 | 205 | 0x0000 0E9A | 2 | ADCD2 interrupt | 14 | 14 |
INT10.15 | 206 | 0x0000 0E9C | 2 | ADCD3 interrupt | 14 | 15 |
INT10.16 | 207 | 0x0000 0E9E | 2 | ADCD4 interrupt | 14 | 16 (Lowest) |
PIE Group 11 Vectors - Muxed into CPU INT11 | ||||||
INT11.1 | 112 | 0x0000 0DE0 | 2 | CLA_1 interrupt | 15 | 1 (Highest) |
INT11.2 | 113 | 0x0000 0DE2 | 2 | CLA_2 interrupt | 15 | 2 |
INT11.3 | 114 | 0x0000 0DE4 | 2 | CLA_3 interrupt | 15 | 3 |
INT11.4 | 115 | 0x0000 0DE6 | 2 | CLA_4 interrupt | 15 | 4 |
INT11.5 | 116 | 0x0000 0DE8 | 2 | CLA_5 interrupt | 15 | 5 |
INT11.6 | 117 | 0x0000 0DEA | 2 | CLA_6 interrupt | 15 | 6 |
INT11.7 | 118 | 0x0000 0DEC | 2 | CLA_7 interrupt | 15 | 7 |
INT11.8 | 119 | 0x0000 0DEE | 2 | CLA_8 interrupt | 15 | 8 |
INT11.9 | 208 | 0x0000 0EA0 | 2 | ADCE event interrupt | 15 | 9 |
INT11.10 | 209 | 0x0000 0EA2 | 2 | ADCE2 interrupt | 15 | 10 |
INT11.11 | 210 | 0x0000 0EA4 | 2 | ADCE3 interrupt | 15 | 11 |
INT11.12 | 211 | 0x0000 0EA6 | 2 | ADCE4 interrupt | 15 | 12 |
INT11.13 | 212 | 0x0000 0EA8 | 2 | Reserved | 15 | 13 |
INT11.14 | 213 | 0x0000 0EAA | 2 | Reserved | 15 | 14 |
INT11.15 | 214 | 0x0000 0EAC | 2 | Reserved | 15 | 15 |
INT11.16 | 215 | 0x0000 0EAE | 2 | Reserved | 15 | 16 (Lowest) |
PIE Group 12 Vectors - Muxed into CPU INT12 | ||||||
INT12.1 | 120 | 0x0000 0DF0 | 2 | XINT3 interrupt | 16 | 1 (Highest) |
INT12.2 | 121 | 0x0000 0DF2 | 2 | XINT4 interrupt | 16 | 2 |
INT12.3 | 122 | 0x0000 0DF4 | 2 | XINT5 interrupt | 16 | 3 |
INT12.4 | 123 | 0x0000 0DF6 | 2 | Reserved | 16 | 4 |
INT12.5 | 124 | 0x0000 0DF8 | 2 | FLSS_INT interrupt | 16 | 5 |
INT12.6 | 125 | 0x0000 0DFA | 2 | VCRC | 16 | 6 |
INT12.7 | 126 | 0x0000 0DFC | 2 | MCANA ECC interrupt | 16 | 7 |
INT12.8 | 127 | 0x0000 0DFE | 2 | MCANA WAKE interrupt | 16 | 8 |
INT12.9 | 216 | 0x0000 0EB0 | 2 | Reserved | 16 | 9 |
INT12.10 | 217 | 0x0000 0EB2 | 2 | Reserved | 16 | 10 |
INT12.11 | 218 | 0x0000 0EB4 | 2 | Reserved | 16 | 11 |
INT12.12 | 219 | 0x0000 0EB6 | 2 | Reserved | 16 | 12 |
INT12.13 | 220 | 0x0000 0EB8 | 2 | AES Interrupt | 16 | 13 |
INT12.14 | 221 | 0x0000 0EBA | 2 | Reserved | 16 | 14 |
INT12.15 | 222 | 0x0000 0EBC | 2 | Reserved | 16 | 15 |
INT12.16 | 223 | 0x0000 0EBE | 2 | Reserved | 16 | 16 (Lowest) |
This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The interrupt allows the application to respond to the error.
An incoming NMI sets a status bit in the NMIFLG register and starts the NMI watchdog counter. This counter is clocked by the SYSCLK, and if the count reaches the value in the NMIWDPRD register, the counter triggers an NMI watchdog reset (NMIWDRS). To prevent this, the NMI handler must clear the flag bit using the NMIFLGCLR register. Once all flag bits are clear, the NMIINT bit in the NMIFLG register can also be cleared to allow future NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI handler vector must be written to the PIE vector table.
The NMI watchdog counter behaves as follows under debug conditions:
CPU Suspended | When the CPU is suspended, the NMI watchdog counter is suspended. |
Run-Free Mode | When the CPU is placed in run-free mode, the NMI watchdog counter resumes operation as normal. |
Real-Time Single-Step Mode | When the CPU is in real-time single-step mode, the NMI watchdog counter is suspended. The counter remains suspended even within real-time interrupts. |
Real-Time Run-Free Mode | When the CPU is in real-time run-free mode, the NMI watchdog counter operates as normal. |
There are several types of hardware errors that can trigger an NMI. Additional information about the error is usually available from the module that detects it.
The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is bypassed, OSCCLK is connected to INTOSC1, and an NMI is fired to the CPU. For more information on missing clock detection, see Section 3.7.12.1.
A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read triggers an NMI. This applies to CPU and DMA reads. Single-bit ECC data errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt. For more information on RAM error detection, see Section 3.11.1.9.
A double-bit ECC data error or single-bit ECC address error in a Flash read triggers an NMI. Single-bit ECC data errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt.
There is a special NMI source that can only be triggered by writing to the SWERR bit in the NMIFLGFRC register. Since the SWERR flag is never set by a real hardware fail, it can be used to implement a self-test mode for the NMI subsystem.
The ERAD module can generate NMI based on different events. This is configurable in the GLBL_NMI_CTL register.
If the CPU tries to execute an illegal instruction, the CPU generates a special interrupt called an illegal instruction trap (ITRAP). This interrupt is non-maskable and has a vector in the PIE vector table. For more information about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and Instruction Set Reference Guide.
The ERRORSTS pin is an ‘always output’ pin and remains high until an error is detected inside the chip. On an error, the ERRORSTS pin goes low (default polarity) until the corresponding internal error status flag for that error source is cleared. Figure 3-4 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin is tri-stated until the chip power rails ramp up to the lower operational limit. As the ERRORSTS pin is an active-low pin (default polarity), users who care about the state of this pin during power-up can connect an external pull-down on this pin.
Following enhancement has been made on this device for ERRORSTS pin logic:
This section explains the clock sources and clock domains on this device, and how to configure them for application use. Figure 3-5 and Figure 3-6 provide an overview of the device's clocking system.
All of the clocks in the device are derived from one of four clock sources.
At power-up, the device is clocked from an on-chip 10MHz oscillator (INTOSC2). INTOSC2 is the primary internal clock source and is the default system clock at reset. INTOSC2 is used to run the boot ROM and can be used as the system clock source for the application. Note that the INTOSC2 frequency tolerance is too loose to meet the timing requirements for CAN. Use of the CAN modules requires an external oscillator. When INTOSC2 is used as the system clock source, GPIO19 (X1) and GPIO18 (X2) are available as GPIO pins.
The device also includes a redundant on-chip 10MHz oscillator (INTOSC1). INTOSC1 is a backup clock source that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is enabled and a missing system clock is detected, the system PLL is bypassed and all system clocks are connected to INTOSC1 automatically. INTOSC1 can also be manually selected as the system clock source for debug purposes.
An additional external clock source is supported on GPIO29 (AUXCLKIN). This must be a single-ended 3.3V external clock as shown in Figure 3-7 and can be used as the clock source for MCAN. Frequency limits and timing requirements are found in the TMS320F28P55x Real-Time Microcontrollers Data Sheet. The external clock can be connected directly to the GPIO29 pin.
The device supports an external clock source (XTAL), which can be used as the main system and CAN bit clock source. Frequency limits and timing requirements can be found in the TMS320F28P55x Real-Time Microcontrollers Data Sheet. External clock sources use the X1/GPIO19 and X2/GPIO18 pins. After power-up, the X1 and X2 pin functionality can be enabled by following the procedure in Section 3.7.6.
Three types of external clock sources are supported:
XTALCR Bit(1) | Operating Mode | GPIO19 Available on X1? | GPIO18 Available on X2? | |
---|---|---|---|---|
OSCOFF | SE | |||
0 | 0 | Crystal Mode: Quartz crystal connected to X1/X2 | No | No |
0 | 1 | Single-Ended Mode: External clock on X1 | No | Yes |
1 | 0 | Oscillator off | Yes | Yes |
1 | 1 | Single-Ended Mode: External clock on X1(2) | No | Yes |
The clock sources discussed in the previous section can be multiplied (using PLL) and divided down to produce the desired clock frequencies for the application. This process produces a set of derived clocks, which are described in this section.
One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the reference clock (OSCCLK) for the CPU and most of the peripherals. OSCCLK can be used directly or applied through the system PLL to reach a higher frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.
The system PLL allows the device to run at the maximum rated operating frequency, and in most applications generates the main system clock. This PLL uses OSCCLK as a reference. PLLRAWCLK is the output of the PLL voltage-controlled oscillator (VCO). For configuration instructions, see Section 3.7.6.
The device clock domains feed the clock inputs of the various modules in the device. They are connected to the derived clocks, either directly or through an additional divider.
The NMI watchdog timer has a clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK can be connected to the system PLL (PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider, which is configured using the SYSCLKDIVSEL register. PLLSYSCLK is gated in HALT mode.
The CPU has a clock (CPUCLK) that is used to clock the CPU and Flash wrapper. This clock is identical to PLLSYSCLK, but is gated when the CPU enters IDLE or HALT mode.
Each peripheral clock has independent clock gating that is controlled by the PCLKCRx registers.