SSZT078 april 2022 DRV8210 , DRV8212 , DRV8220 , DRV8243-Q1 , DRV8244-Q1 , DRV8245-Q1
Nicholas Oborny
Semiconductor packaging techniques have evolved in order to adapt to the smaller chip sizes made possible by technological advances, as well as increased power dissipation and growing demands for power density. Flip chip on leadframe (FCOL) packaging technologies have become increasingly popular given their technical benefits and efficient use of printed circuit board (PCB) area. In this article, I’ll give a short overview of FCOL for both small outline transistor (SOT)- and quad flat no-lead (QFN)-type packages, and the adoption of these packaging techniques for motor-drive applications.
FCOL is not a specific type of package such as SOT or QFN; instead, it describes a method of die-to-package interconnection. Traditional methods connect (or bond) a physical wire from the silicon die to the package leadframe to create an electrical connection, as shown in Figure 1.
Although there have been numerous advancements in bonding techniques over the decades, FCOL is a fundamentally different method of die-to-package interconnection. Figure 2 shows the direct mounting of the inverted (or flipped) silicon die to the leadframe (hence the name “flip chip on lead”). The die-to-package connection is through a series of copper posts that attach directly to the top-side metal layer of the die.
Eliminating the wire-bond interconnection achieves multiple benefits, including:
Improvements in the reliability, manufacturing costs and performance of FCOL packaging have enabled its adoption into increasingly diverse application spaces. In motor drives, FCOL packaging has proven useful in reducing package form factors, lowering costs and improving the thermal capability of both compact low-voltage drivers and larger high-power drivers with low drain-to-source on-resistance specifications.
In low-voltage drivers such as the DRV8210, DRV8212 and DRV8220, the SOT-563 package size (an FCOL SOT, shown in Figure 3) is smaller than any previous generation, without resorting to complex and expensive-to-assemble wafer chip-scale or ball-grid-array packages. Although SOT packages with wire bonds have been popular in motor-drive applications, the wire-bond clearances restrict the maximum allowable die sizes for these packages. Additionally, the lack of a thermal pad minimizes thermal performance. FCOL in SOT packaging removes any wire clearance restrictions and improves thermal performance vs. traditional wire-bond SOT packages.
In high-power integrated drivers such as the DRV8243-Q1, DRV8244-Q1 and DRV8245-Q1, TI’s HotRod™ QFN (FCOL QFN) packaging enables a smaller package footprint with respect to die size, resulting in some of the lowest on-resistance automotive drivers on the market (through removal of the wire-bond interconnects). In the past, high-power drivers required large packages in order to accommodate the increased die size from the large power metal-oxide semiconductor field-effect transistors, and the associated wire bonds required to transfer current from the silicon die to the package. HotRod QFN reduces the packaging size for these high-power drivers by more than half, while still maintaining the current capability necessary for automotive applications.
The demand for efficient packaging solutions in response to continued reductions in semiconductor technology has led to a wide array of novel packaging solutions. These package types enable smaller form factors, lower cost and higher performance to achieve engineering goals in industrial and automotive applications. Because there’s so much more to say about FCOL packaging, I’ll leave some additional resources below for further investigation.
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