The LM15851 device is a wideband sampling and digital tuning device. Texas Instruments' giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.
The LM15851 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM15851 | VQFN (68) | 10.00 mm × 10.00 mm |
Changes from D Revision (July 2015) to E Revision
Changes from C Revision (September 2014) to D Revision
Changes from B Revision (February 2014) to C Revision
Changes from A Revision (February 2014) to B Revision
Changes from * Revision (January 2014) to A Revision
PIN | EQUIVALENT CIRCUIT | TYPE | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
ANALOG | ||||
RBIAS+ | 1 | ![]() |
I/O | External Bias Resistor Connections
External bias resistor terminals. A 3.3 kΩ (±0.1%) resistor should be connected between RBIAS+ and RBIAS–. The RBIAS resistor is used as a reference for internal circuits which affect the linearity of the converter. The value and precision of this resistor should not be compromised. These pins must be isolated from all other signals and grounds. |
RBIAS– | 2 | |||
TDIODE– | 63 | ![]() |
Passive | Temperature Diode
These pins are the positive (anode) and negative (cathode) diode connections for die temperature measurements. Leave these pins unconnected if they are not used. See the Built-In Temperature Monitor Diode section for more details. |
TDIODE+ | 64 | |||
VBG | 68 | ![]() |
O | Bandgap Output Voltage
This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF. Leave this pin unconnected if it is not used in the application. See the The Reference Voltage section for more details. |
VCMO | 3 | O | Common Mode Voltage
The voltage output at this pin must be the common-mode input voltage at the VIN+ and VIN– pins when DC coupling is used. This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF. Leave this pin unconnected if it is not used in the application. |
|
VIN+ | 8 | ![]() |
I | Signal Input
The differential full-scale input range is determined by the full-scale voltage adjust register. An internal peaking inductor (LPEAK) of 5 nH is included for parasitic compensation. |
VIN– | 9 | |||
DATA | ||||
DS0− | 32 | ![]() |
O | Data
CML These pins are the high-speed serialized-data outputs with user-configurable pre-emphasis. These outputs must always be terminated with a 100-Ω differential resistor at the receiver. |
DS0+ | 33 | |||
DS1– | 35 | |||
DS1+ | 36 | |||
DS2– | 38 | |||
DS2+ | 39 | |||
DS3– | 41 | |||
DS3+ | 42 | |||
DS4– | 44 | |||
DS4+ | 45 | |||
GROUND, RESERVED, DNC | ||||
DNC | 67 | — | Do Not Connect
Do not connect DNC to any circuitry, power, or ground signals. |
|
RSV | 66 | ![]() |
— | Reserved
Connect to Ground or Leave Unconnected: This reserved pin is a logic input for possible future device versions. It is recommended to connect this pin to ground. Floating this pin is also permissible. |
RSV2 | 61 | — | Reserved
Connect to Ground Connect this reserved input pin to ground for proper operation. |
|
Thermal Pad | — | Ground (GND)
The exposed pad on the bottom of the package is the ground return for all supplies. This pad must be connected with multiple vias to the printed circuit board (PCB) ground planes to ensure proper electrical and thermal performance. The exposed center pad on the bottom of the package must be thermally and electrically connected (soldered) to a ground plane to ensure rated performance. |
||
LVCMOS | ||||
NCO_0 | 47, 48 | ![]() |
I | NCO ConfigSelect
These three pin pairs allow the host device to select the specific NCO frequency or phase accumulator that is active. Each pair must be connected together and driven with a common 1.8-V LVCMOS signal. Connect these inputs to GND if they are not used in the application. |
NCO_1 | 50, 51 | |||
NCO_2 | 53, 54 | |||
OR_T0 | 25 | ![]() |
O | Over-Range
Over-range detection status for T0 and T1 thresholds. Leave these pins unconnected if they are not used in the application. |
OR_T1 | 26 | |||
SCLK | 58 | ![]() |
I | Serial Interface Clock
This pin functions as the serial-interface clock input which clocks the serial data in and out. The Using the Serial Interface section describes the serial interface in more detail. |
SDI | 57 | I | Serial Data In
This pin functions as the serial-interface data input. The Using the Serial Interface section describes the serial interface in more detail. |
|
SYNC~ | 30 | I | SYNC~
This pin provides the JESD204B-required synchronizing request input. A logic-low applied to this input initiates a lane alignment sequence. The choice of LVCMOS or differential SYNC~ is selected through bit 6 of the configuration register 0x202h. Connect this input to GND or VA19 if differential SYNC~ input is used. |
|
SCS | 59 | I | Serial Chip Select (active low)
This pin functions as the serial-interface chip select. The Using the Serial Interface section describes the serial interface in more detail. |
|
SDO | 56 | ![]() |
O | Serial Data Out
This pin functions as the serial-interface data output. The Using the Serial Interface section describes the serial interface in more detail. |
DIFFERENTIAL INPUT | ||||
DEVCLK+ | 15 | ![]() |
I | Device Clock Input
The differential device clock signal must be AC coupled to these pins. The input signal is sampled on the rising edge of CLK. |
DEVCLK– | 16 | |||
SYSREF+ | 19 | I | SYSREF
The differential periodic waveform on these pins synchronizes the device per JESD204B. If JESD204B subclass 1 synchronization is not required and these inputs are not utilized they may be left unconnected. In that case ensure SysRef_Rcvr_En=0 and SysRef_Pr_En=0. |
|
SYSREF– | 20 | |||
SYNC~+ | 22 | I | SYNC~
This differential input provides the JESD204B-required synchronizing request input. A differential logic-low applied to these inputs initiates a lane alignment sequence. For differential SYNC~ usage, leave unconnected if SYNC_DIFFSEL = 0. These inputs may be left unconnected if they are not used for the SYNC~function. |
|
SYNC~- | 23 | |||
POWER | ||||
VA12 | 6 | — | Analog 1.2 V power supply pins
Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling. |
|
11 | ||||
14 | ||||
17 | ||||
18 | ||||
21 | ||||
65 | ||||
VA19 | 4 | — | Analog 1.9 V power supply pins
Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling. |
|
7 | ||||
10 | ||||
13 | ||||
24 | ||||
27 | ||||
60 | ||||
62 | ||||
VD12 | 28 | — | Digital 1.2 V power supply pins
Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling. |
|
31 | ||||
34 | ||||
37 | ||||
40 | ||||
43 | ||||
46 | ||||
49 | ||||
52 | ||||
55 | ||||
VNEG | 5 | I | VNEG
These pins must be decoupled to ground with a 0.1-µF ceramic capacitor near each pin. These power input pins must be connected to the VNEG_OUT pin with a low resistance path. The connections must be isolated from any noisy digital signals and must also be isolated from the analog input and clock input pins. |
|
12 | ||||
VNEG_OUT | 29 | O | VNEG_OUT
The voltage on this output can range from –1V to +1V. This pin must be decoupled to ground with a 4.7-µF, low ESL, low ESR multi-layer ceramic chip capacitor and connected to the VNEG input pins. This voltage must be isolated from any noisy digital signals, clocks, and the analog input. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage | 1.2-V supply | VA12, VD12 | 1.4 | V | |
1.9-V supply | VA19 | 2.2 | |||
1.2-V supply difference between VA12 and VD12 | –200 | 200 | mV | ||
Voltage | On any input pin (except VIN+ or VIN–) | –0.15 | V(VA19) + 0.15 | V | |
On VIN+ or VIN– | 0 | 2 | |||
Voltage difference | |(VIN+) – (VIN–)|(2) | 2 | V | ||
|(DEVCLK+) – (DEVCLK–)| | 2 | ||||
|(SYSREF+) – (SYSREF–)| | 2 | ||||
|(~SYNC+) – (~SYNC–)| | 1 | ||||
RF input power, PI | On VIN+, VIN–, with proper input common mode maintained. FIN ≥ 3 GHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 0 or 1 | 11.07 | dBm | ||
On VIN+, VIN–, with proper input common mode maintained. FIN = 1 GHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 1 | 14.95 | ||||
On VIN+, VIN–, with proper input common mode maintained. FIN ≤ 100 MHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 1 | 20.97 | ||||
Input current | At any pin other than VIN+ or VIN–(4) | –25 | 25 | mA | |
VIN+ or VIN– | –50 | 50 | mA DC | ||
Package(4) (sum of absolute value of all currents forced in or out, not including power supply current) | 100 | mA | |||
Junction temperature, TJ | Power applied. Verified by High Temperature Operation Life testing to 1000 hours. | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
THERMAL METRIC(1) | LM15851 | UNIT | |
---|---|---|---|
NKE (VQFN) | |||
68 PINS | |||
RθJA | Thermal resistance, junction-to-ambient | 19.8 | °C/W |
RθJCbot | Thermal resistance, junction-to-case (bottom) | 2.7 | °C/W |
ψJB | Characterization parameter, junction-to-board | 9.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DYNAMIC PERFORMANCE CHARACTERISTICS | |||||||
IMD3 | Third-order intermodulation distortion | F1 = 2110 MHz at −13 dBFS F2 = 2170 MHz at −13 dBFS |
–64 | dBc | |||
DECIMATE-BY-4 MODE | |||||||
SNR1 | Signal-to-noise ratio, integrated across DDC alias protected output bandwidth Input frequency-dependent interleaving spurs included |
FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | 59.9 | dBFS | ||
TA = TMIN to TMAX | 56.2 | ||||||
TA = 25°C, calibration = BG | 59.2 | ||||||
TA = TMIN to TMAX, calibration = BG | 53.3 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode | 56.4 | ||||||
SNR2 | Signal-to-noise ratio, integrated across DDC alias protected output bandwidth Input frequency-dependent interleaving spurs excluded |
FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C(4) | 60.1 | dBFS | ||
TA = TMIN to TMAX(4) | 56.7 | ||||||
TA = 25°C, calibration = BG (4) | 60.2 | ||||||
TA = TMIN to TMAX, calibration = BG(4) | 56.7 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode(4) | 57 | ||||||
SINAD1 | Signal-to-noise and distortion ratio, integrated across DDC alias protected output bandwidth Input frequency-dependent interleaving spurs included |
FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | 59.9 | dBFS | ||
TA = TMIN to TMAX | 55.9 | ||||||
TA = 25°C, calibration = BG | 59.2 | ||||||
TA = TMIN to TMAX, calibration = BG | 53.1 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode | 56.4 | ||||||
SINAD2 | Signal-to-noise and distortion ratio, integrated across DDC alias protected output bandwidth Interleaving spurs excluded |
FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C(4) | 60.1 | dBFS | ||
TA = TMIN to TMAX(4) | 56.3 | ||||||
TA = 25°C, calibration = BG (4) | 60.1 | ||||||
TA = TMIN to TMAX, calibration = BG(4) | 56.4 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode(4) | 57 | ||||||
ENOB1 | Effective number of bits, integrated across DDC alias protected output bandwidth Interleaving spurs included |
FIN = 600 MHz, –1 dBFS, Decimate-by-4 mode | TA = 25°C | 9.7 | Bits | ||
TA = TMIN to TMAX | 9.0 | ||||||
TA = 25°C, calibration = BG | 9.5 | ||||||
TA = TMIN to TMAX, calibration = BG | 8.5 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode | 9.1 | ||||||
ENOB2 | Effective number of bits, integrated across DDC alias protected output bandwidth Interleaving spurs excluded |
FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C(4) | 9.7 | Bits | ||
TA = TMIN to TMAX(4) | 9.0 | ||||||
TA = 25°C, calibration = BG (4) | 9.7 | ||||||
TA = TMIN to TMAX, calibration = BG(4) | 9.1 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode(4) | 8.5 | ||||||
SFDR1 | Spurious-free dynamic range across entire Nyquist bandwidth Interleaving spurs included |
FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | 70.1 | dBFS | ||
TA = TMIN to TMAX | 59.2 | ||||||
TA = 25°C, calibration = BG | 62.9 | ||||||
TA = TMIN to TMAX, calibration = BG | 51.8 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode | 66.4 | ||||||
SFDR2 | Spurious-free dynamic range across entire Nyquist bandwidth Interleaving spurs excluded |
FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C(4) | 71.6 | dBFS | ||
TA = TMIN to TMAX(4) | 60 | ||||||
TA = 25°C, calibration = BG (4) | 74.8 | ||||||
TA = TMIN to TMAX, calibration = BG(4) | 62.9 | ||||||
FIN = 2400 MHz, –1 dBFS, Decimate-by-4 mode(4) | 80.4 | ||||||
ƒS/2 | Interleaving offset spur at ½ sampling rate(5) | FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | –72 | dBFS | ||
TA = TMIN to TMAX | –56 | ||||||
TA = 25°C, calibration = BG | –65 | ||||||
TA = TMIN to TMAX, calibration = BG | –50.5 | ||||||
ƒS/4 | Interleaving offset spur at ¼ sampling rate(5) | FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | –68 | dBFS | ||
TA = TMIN to TMAX | –55 | ||||||
TA = 25°C, calibration = BG | –62 | ||||||
TA = TMIN to TMAX, calibration = BG | –47.4 | ||||||
ƒS/2 – FIN | Interleaving spur at ½ sampling rate – input frequency(5) | FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | –75 | dBFS | ||
TA = TMIN to TMAX | –62.3 | ||||||
TA = 25°C, calibration = BG | –70 | ||||||
TA = TMIN to TMAX, calibration = BG | –51.5 | ||||||
ƒS/4 + FIN | Interleaving spur at ¼ sampling rate + input frequency(5) | FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | –73 | dBFS | ||
TA = TMIN to TMAX | –58.9 | ||||||
TA = 25°C, calibration = BG | –65 | ||||||
TA = TMIN to TMAX, calibration = BG | –52.8 | ||||||
ƒS/4 – FIN | Interleaving spur at ¼ sampling rate – input frequency(5) | FIN = 600 MHz, –1 dBFS, Decimate-by-4 mode | TA = 25°C | –78 | dBFS | ||
TA = TMIN to TMAX | –60.4 | ||||||
TA = 25°C, calibration = BG | –65 | ||||||
TA = TMIN to TMAX, calibration = BG | –52.3 | ||||||
THD | Total harmonic distortion(5) | FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | –70 | dBFS | ||
TA = TMIN to TMAX | –59.5 | ||||||
TA = 25°C, calibration = BG | –73 | ||||||
TA = TMIN to TMAX, calibration = BG | –60 | ||||||
HD2 | Second harmonic distortion(5) | FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | –83 | dBFS | ||
TA = TMIN to TMAX | –62 | ||||||
TA = 25°C, calibration = BG | –78 | ||||||
TA = TMIN to TMAX, calibration = BG | –62.5 | ||||||
HD3 | Third harmonic distortion(5) | FIN = 600 MHz, –1 dBFS, decimate-by-4 mode | TA = 25°C | –72 | dBFS | ||
TA = TMIN to TMAX | –59.5 | ||||||
TA = 25°C, calibration = BG | –82 | ||||||
TA = TMIN to TMAX, calibration = BG | –62 | ||||||
DECIMATE-BY-8 MODE | |||||||
SNR1 | Signal-to-noise ratio, integrated across DDC output bandwidth Interleaving spurs included |
FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | 63 | dBFS | |||
Calibration = BG | 61.6 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode | 54.6 | ||||||
SNR2 | Signal-to-noise ratio, integrated across DDC output bandwidth Interleaving spurs excluded |
FIN = 600 MHz, –1 dBFS, decimate-by-8 mode(4) | 63.3 | dBFS | |||
Calibration = BG | 63.3 | ||||||
SINAD1 | Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Interleaving spurs included |
FIN = 600 MHz, –1 dBFS, Decimate-by-8 mode | 63 | dBFS | |||
Calibration = BG | 61.6 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode | 54.6 | ||||||
SINAD2 | Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Interleaving spurs excluded |
FIN = 600 MHz, –1 dBFS, decimate-by-8 mode(4) | 63.3 | dBFS | |||
Calibration = BG | 63.3 | ||||||
ENOB1 | Effective number of bits, integrated across DDC output bandwidth Interleaving spurs included |
FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | 10.2 | Bits | |||
Calibration = BG | 10.0 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode | 8.8 | ||||||
ENOB2 | Effective number of bits, integrated across DDC output bandwidth Interleaving spurs excluded |
FIN = 600 MHz, –1 dBFS, decimate-by-8 mode(5) | 10.2 | Bits | |||
Calibration = BG | 10.2 | ||||||
SFDR1 | Spurious-free dynamic range Interleaving Spurs Included |
FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | 74.9 | dBFS | |||
Calibration = BG | 68.3 | ||||||
SFDR2 | Spurious-free dynamic range Interleaving spurs excluded |
FIN = 600 MHz, –1 dBFS, decimate-by-8 mode(5) | 77.8 | dBFS | |||
Calibration = BG | 77.8 | ||||||
ƒS/2 | Interleaving offset spur at ½ sampling rate(5) | FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | –73 | dBFS | |||
Calibration = BG | –72 | ||||||
ƒS/4 | Interleaving offset spur at ¼ sampling rate(5) | FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | –70 | dBFS | |||
Calibration = BG | –66 | ||||||
ƒS/2 – FIN | Interleaving spur at ½ sampling rate – input frequency(5) | FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | –76 | dBFS | |||
Calibration = BG | –67 | ||||||
ƒS/4 + FIN | Interleaving spur at ¼ sampling rate + input frequency(5) | FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | –72 | dBFS | |||
Calibration = BG | –64 | ||||||
ƒS/4 – FIN | Interleaving spur at ¼ sampling rate – input frequency(5) | FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | –74 | dBFS | |||
Calibration = BG | –67 | ||||||
THD | Total harmonic distortion(6) | FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | –70 | dBFS | |||
Calibration = BG | –72 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode | –71 | ||||||
HD2 | Second harmonic distortion(6) | FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | –80 | dBFS | |||
Calibration = BG | –79 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode | –78 | ||||||
HD3 | Third harmonic distortion(6) | FIN = 600 MHz, –1 dBFS, decimate-by-8 mode | –74 | dBFS | |||
Calibration = BG | –80 | ||||||
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode | –-77 | ||||||
DDC CHARACTERISTICS | |||||||
Alias protection(2) | 80 | dB | |||||
Alias protected bandwidth(2) | 80 | % of output BW | |||||
SFDR-DDC | Spurious-free dynamic range of digital down-converter(2) | 100 | dB | ||||
Implementation loss(2) | 0.5 | dB | |||||
ANALOG INPUT CHARACTERISTICS | |||||||
VID(VIN) | Full-scale analog-differential input range | Minimum FSR setting(6) | 500 | mVPP | |||
Default FSR setting, TA = TMIN to TMAX | 650 | 725 | 800 | ||||
Maximum FSR setting(6) | 950 | ||||||
CI(VIN) | Analog input capacitance(2) | Differential | 0.05 | pF | |||
Each input pin to ground | 1.5 | pF | |||||
RID(VIN) | Differential input resistance | 80 | 95 | 110 | Ω | ||
FPBW | Full power bandwidth | –3 dB — calibration = BG | 2.8 | GHz | |||
–3 dB — calibration = FG | 3.2 | ||||||
Gain flatness | DC to 2 GHz | 1.2 | dB | ||||
2 GHz to 4 GHz | 3.8 | ||||||
DC to 2 GHz — calibration = BG | 1.5 | ||||||
2 GHz to 4 GHz — calibration = BG | 4.5 | ||||||
ANALOG OUTPUT CHARACTERISTICS (VCMO, VBG) | |||||||
V(VCMO) | Common-mode output voltage | I(VCMO) = ±100 µA, TA = 25°C | 1.225 | V | |||
I(VCMO) = ±100 µA, TA = TMIN to TMAX | 1.185 | 1.265 | |||||
TCVO(VCMO) | Common-mode output-voltage temperature coefficient | TA = TMIN to TMAX | -21 | ppm/°C | |||
C(LOAD_VCMO) | Maximum VCMO output load capacitance | 80 | pF | ||||
VO(BG) | Bandgap reference output voltage | I(BG) = ±100 µA, TA = 25°C | 1.248 | V | |||
I(BG) = ±100 µA, TA = TMIN to TMAX | 1.195 | 1.3 | |||||
TCVref(BG) | Bandgap reference voltage temperature coefficient | TA = TMIN to TMAX, I(BG) = ±100 µA |
0 | ppm/°C | |||
C(LOAD_BG) | Maximum bandgap reference output load capacitance | 80 | pF | ||||
TEMPERATURE DIODE CHARACTERISTICS | |||||||
V(TDIODE) | Temperature diode voltage slope | Offset voltage (approx. 0.77 V) varies with process and must be measured for each part. Offset measurement should be done with PowerDown=1 to minimize device self-heating. | 100-µA forward current Device active |
–1.6 | mV/°C | ||
100-µA forward current Device in power-down |
–1.6 | mV/°C | |||||
CLOCK INPUT CHARACTERISTICS (DEVCLK±, SYSREF±, SYNC~) | |||||||
VID(CLK) | Differential clock input level | Sine wave clock, TA = TMIN to TMAX | 0.4 | 0.6 | 2 | VPP | |
Square wave clock, TA = TMIN to TMAX | 0.4 | 0.6 | 2 | VPP | |||
II(CLK) | Input current | VI = 0 or VI = VA | ±1 | µA | |||
CI(CLK) | Input capacitance(2) | Differential | 0.02 | pF | |||
Each input to ground | 1 | pF | |||||
RID(CLK) | Differential input resistance | TA = 25°C | 95 | Ω | |||
TA = TMIN to TMAX | 80 | 110 | Ω | ||||
CML OUTPUT CHARACTERISTICS (DS0–DS7±) | |||||||
VOD | Differential output voltage | Assumes ideal 100-Ω load Measured differentially Default pre-emphasis setting |
280 | 305 | 330 | mV peak | |
VO(ofs) | Output offset voltage | 0.6 | V | ||||
IOS | Output short-circuit current | Output+ and output– shorted together | ±6 | mA | |||
Output+ or output– shorted to 0 V | 12 | ||||||
ZOD | Differential output impedance | 100 | Ω | ||||
LVCMOS INPUT CHARACTERISTICS (SDI, SCLK, SCS, SYNC~) | |||||||
VIH | Logic high input voltage | See (6) | 0.83 | V | |||
VIL | Logic low input voltage | See (6) | 0.4 | V | |||
CI | Input capacitance(2)(7) | Each input to ground | 1 | pF | |||
LVCMOS OUTPUT CHARACTERISTICS (SDO, OR_T0, OR_T1) | |||||||
VOH | CMOS H level output | IOH = –400 µA(6) | 1.65 | 1.9 | V | ||
VOL | CMOS L level output | IOH = 400 µA(6) | 0.01 | 0.15 | V | ||
POWER SUPPLY CHARACTERISTICS | |||||||
I(VA19) | Analog 1.9-V supply current | PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 | 560 | 607 | mA | ||
I(VA12) | Analog 1.2-V supply current | PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 | 377 | 428 | mA | ||
I(VD12) | Digital 1.2-V supply current | PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 | 541 | 826 | mA | ||
PC | Power consumption | PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 | 2.17 | 2.66 | W | ||
PD = 1 | < 50 | mW |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
DEVICE (SAMPLING) CLOCK | ||||||
ƒ(DEVCLK) | Input DEVCLK frequency | Sampling rate is equal to clock input | 1 | 4 | GHz | |
td(A) | Sampling (aperture) delay | Input CLK transition to sampling instant | 0.64 | ns | ||
t(AJ) | Aperture jitter | 0.1 | ps RMS | |||
t(LAT_DDC) | ADC core and DDC latency(2) | Decimation = 4, DDR = 1, P54 = 0 | 292 | t(DEVCLK) | ||
Decimation = 4, DDR = 1, P54 = 1 | 284 | |||||
Decimation = 8, DDR = 0, P54 = 0 | 384 | |||||
Decimation = 8, DDR = 0, P54 = 1 | 368 | |||||
Decimation = 8, DDR = 1, P54 = 0 | 392 | |||||
Decimation = 8, DDR = 1, P54 = 1 | 368 | |||||
Decimation = 10, DDR = 0, P54 = 0 | 386 | |||||
Decimation = 10, DDR = 1, P54 = 0 | 386 | |||||
Decimation = 16, DDR = 0, P54 = 0 | 608 | |||||
Decimation = 16, DDR = 0, P54 = 1 | 560 | |||||
Decimation = 16, DDR = 1, P54 = 0 | 608 | |||||
Decimation = 16, DDR = 1, P54 = 1 | 560 | |||||
Decimation = 20, DDR = 0, P54 = 0 | 568 | |||||
Decimation = 20, DDR = 1, P54 = 0 | 568 | |||||
Decimation = 32, DDR = 0, P54 = 0 | 1044 | |||||
Decimation = 32, DDR = 0, P54 = 1 | 948 | |||||
Decimation = 32, DDR = 1, P54 = 0 | 1044 | |||||
JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1) | ||||||
td(LMFC) | SYSREF to LMFC delay Functional delay between SYSREF assertion latched and LMFC frame boundary(2) |
All decimation modes | 40 | t(DEVCLK) | ||
td(TX) | LMFC to frame boundary delay - decimation modes Functional delay from LMFC frame boundary to beginning of next multi-frame in transmitted data(3) |
Decimation = 4, DDR = 1, P54 = 0 | 52.7 | t(DEVCLK) | ||
Decimation = 4, DDR = 1, P54 = 1 | 43.9 | |||||
Decimation = 8, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 8, DDR = 0, P54 = 1 | 51.5 | |||||
Decimation = 8, DDR = 1, P54 = 0 | 52.7 | |||||
Decimation = 8, DDR = 1, P54 = 1 | 43.9 | |||||
Decimation = 10, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 10, DDR = 1, P54 = 0 | 52.7 | |||||
Decimation = 16, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 16, DDR = 0, P54 = 1 | 51.5 | |||||
Decimation = 16, DDR = 1, P54 = 0 | 52.7 | |||||
Decimation = 16, DDR = 1, P54 = 1 | 43.9 | |||||
Decimation = 20, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 20, DDR = 1, P54 = 0 | 52.7 | |||||
Decimation = 32, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 32, DDR = 0, P54 = 1 | 51.5 | |||||
Decimation = 32, DDR = 1, P54 = 0 | 52.7 | |||||
tsu(SYNC~-F) | SYNC~ to LMFC setup time(1)
Required SYNC~ setup time relative to the internal LMFC boundary. |
40 | t(DEVCLK) | |||
th(SYNC~-F) | SYNC~ to LMFC hold time(1)
Required SYNC~ hold time relative to the internal LMFC boundary. |
–8 | ||||
t(SYNC~) | SYNC~ assertion time Required SYNC~ assertion time before deassertion to initiate a link resynchronization. |
4 | Frame clock cycles | |||
td(LMFC) | Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary | 40 | t(DEVCLK) | |||
t(ILA) | Duration of initial lane alignment sequence | 4 | Multi-frame clock cycles | |||
SYSREF | ||||||
tsu(SYS) | Setup time SYSREF relative to DEVCLK rising edge(6) | 40 | ps | |||
th(SYS) | Hold time SYSREF relative to DEVCLK rising edge(6) | 40 | ps | |||
t(PH_SYS) | SYSREF assertion duration after rising edge event. | 8 | t(DEVCLK) | |||
t(PL_SYS) | SYSREF deassertion duration after falling edge event. | 8 | t(DEVCLK) | |||
t(SYS) | Period SYSREF± | DDR = 0, P54 = 0 | K × F × 10 | t(DEVCLK) | ||
DDR = 0, P54 = 1 | K × F × 8 | |||||
DDR = 1, P54 = 0 | K × F × 5 | |||||
DDR = 1, P54 = 1 | K × F × 4 | |||||
SERIAL INTERFACE (REFER TO Figure 2) | ||||||
ƒ(SCK) | Serial clock frequency(2) | 20 | MHz | |||
t(PH) | Serial clock high time | 20 | ns | |||
t(PL) | Serial clock low time | 20 | ns | |||
tsu | Serial-data to serial-clock rising setup time(2) | 10 | ns | |||
th | Serial-data to serial clock rising hold time(2) | 10 | ns | |||
t(CSS) | SCS-to-serial clock rising setup time | 10 | ns | |||
t(CSH) | SCS-to-serial clock falling hold time | 10 | ns | |||
t(IAG) | Inter-access gap | 10 | ns |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
DEVICE (SAMPLING) CLOCK | ||||||
td(A) | Sampling (aperture) delay | Input CLK transition to sampling instant | 0.64 | ns | ||
t(AJ) | Aperture jitter | 0.1 | ps RMS | |||
CALIBRATION TIMING CHARACTERISTICS (REFER TO THE CALIBRATION SECTION) | ||||||
t(CAL) | Calibration cycle time | Calibration = FG, T_AUTO=1 | 227 × 106 | t(DEVCLK) | ||
Calibration = FG, T_AUTO=0 | 102 × 106 | |||||
JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1) | ||||||
td(LMFC) | SYSREF to LMFC delay Functional delay between SYSREF assertion latched and LMFC frame boundary(2) |
All decimation modes | 40 | t(DEVCLK) | ||
td(TX) | LMFC to frame boundary delay - decimation modes Functional delay from LMFC frame boundary to beginning of next multi-frame in transmitted data(3) |
Decimation = 4, DDR = 1, P54 = 0 | 52.7 | t(DEVCLK) | ||
Decimation = 4, DDR = 1, P54 = 1 | 43.9 | |||||
Decimation = 8, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 8, DDR = 0, P54 = 1 | 51.5 | |||||
Decimation = 8, DDR = 1, P54 = 0 | 52.7 | |||||
Decimation = 8, DDR = 1, P54 = 1 | 43.9 | |||||
Decimation = 10, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 10, DDR = 1, P54 = 0 | 52.7 | |||||
Decimation = 16, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 16, DDR = 0, P54 = 1 | 51.5 | |||||
Decimation = 16, DDR = 1, P54 = 0 | 52.7 | |||||
Decimation = 16, DDR = 1, P54 = 1 | 43.9 | |||||
Decimation = 20, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 20, DDR = 1, P54 = 0 | 52.7 | |||||
Decimation = 32, DDR = 0, P54 = 0 | 60.7 | |||||
Decimation = 32, DDR = 0, P54 = 1 | 51.5 | |||||
Decimation = 32, DDR = 1, P54 = 0 | 52.7 | |||||
td(LMFC) | Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary | 40 | t(DEVCLK) | |||
t(ILA) | Duration of initial lane alignment sequence | 4 | Multi-frame clock cycles |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SERIAL DATA OUTPUTS | ||||||
Serialized output bit rate | 1 | 10 | Gbps | |||
Serialized output bit rate | DDR = 0, P54 = 0 | ƒS | ||||
DDR = 0, P54 = 1 | 1.25 × ƒS | |||||
DDR = 1, P54 = 0 | 2 × ƒS | |||||
DDR = 1, P54 = 1 | 2.5 × ƒS | |||||
tTLH | LH transition time — differential | 10% to 90%, 8 Gbps | 35 | ps | ||
tTHL | HL transition time — differential | 10% to 90%, 8 Gbps | 35 | ps | ||
UI | Unit interval | 8 Gbps serial rate | 125 | ps | ||
DDJ | Data dependent jitter | 8 Gbps serial rate | 11.3 | ps | ||
RJ | Random Jitter | 8 Gbps serial rate | 1.4 | ps | ||
SERIAL INTERFACE | ||||||
t(OZD) | SDO tri-state to driven | See Figure 2 | 5 | ns | ||
t(ODZ) | SDO driven to tri-state | 2.5 | 5 | ns | ||
t(OD) | SDO output delay | 20 | ns |
FIN = 608 MHz |
Decimate by 16 mode | FIN = 608 MHz |
FIN = 608 MHz |
Decimate by 16 mode | FIN = 608 MHz |
FIN = 608 MHz |
Decimate by 16 mode | FIN = 608 MHz |
Decimate by 16 mode | FIN = 608 MHz |
Foreground calibration mode |
FIN = 2483 MHz |
Decimate by 16 mode | FIN = 608 MHz |
FIN = 2483 MHz |
Decimate by 16 mode | FIN = 608 MHz |
Decimate by 16 mode | FIN = 608 MHz |
FIN = 608 MHz |
Decimate by 16 mode | FIN = 608 MHz |
Background calibration mode |