The SN65LVPE502x devices are dual-channel, single-lane USB 3.0 redriver and signal conditioners supporting data rates of 5 Gbps. The devices comply with USB 3.0 specification revision 1.0 supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN65LVPE502A | RLL (24) | 3.00 mm × 3.00 mm |
SN65LVPE502A, SN65LVPE502B |
RGE (24) | 4.00 mm × 4.00 mm |
Changes from B Revision (April 2012) to C Revision
Changes from A Revision (March 2012) to B Revision
Changes from * Revision (March 2012) to A Revision
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | SN65LVPE502A | SN65LVPE502B | ||
HIGH SPEED DIFFERENTIAL I/O PINS | ||||
Host_RX1– | 8 | 20 | I | CML, inverting differential input for CH1. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 host side. |
Host_RX1+ | 9 | 19 | I | CML, noninverting differential input for CH1. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 host side. |
Device_RX2– | 20 | 8 | I | CML, inverting differential input for CH2. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 Device side. |
Device_RX2+ | 19 | 9 | I | CML, noninverting differential input for CH2. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 Device side. |
Device_TX1– | 23 | 11 | O | CML, inverting differential output for CH1. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Device side. |
Device_TX1+ | 22 | 12 | O | CML, noninverting differential output for CH1. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Device side. |
Host_TX2– | 11 | 23 | O | CML, inverting differential output for CH2. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Host side. |
Host_TX2+ | 12 | 22 | O | CML, noninverting differential output for CH2. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Host side. |
DEVICE CONTROL PINS | ||||
EN_RXD | 5 | 17 | I | LVCMOS, sets device operation modes per Table 4; internally pulled to VCC. |
RSVD | 14 | — | I | LVCMOS; RSVD. Can be left as No-Connect. |
NC | 7, 24 | 2, 3, 4, 6, 14, 18, 24 | — | Pads are not internally connected. |
EQ CONTROL PINS(2) | ||||
DE1, DE2 | 3, 16 | 16, 5 | I | LVCMOS, selects de-emphasis settings for CH1 and CH2 per Table 4; internally tied to VCC/2. |
EQ1, EQ2 | 2, 17 | 15, 7 | I | LVCMOS, selects equalization settings for CH1 and CH2 per Table 4, internally tied to VCC/2. |
OS1, OS2 | 4, 15 | — | I | LVCMOS, selects output amplitude for CH1 and CH2 per Table 4, internally tied to VCC/2. |
POWER PINS(3) | ||||
GND | 6, 10, 18, 21, Thermal Pad | 10, 21, Thermal Pad | P | Supply ground |
VCC | 1,13 | 1, 13 | P | Positive supply; must be 3.3 V ±10% |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
HIGH SPEED DIFFERENTIAL I/O PINS | |||
Host_RX1– | 19 | I | CML, inverting differential input for CH1. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 host side. |
Host_RX1+ | 20 | I | CML, noninverting differential input for CH1. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 host side. |
Device_RX2– | 8 | I | CML, inverting differential input for CH2. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 Device side. |
Device_RX2+ | 7 | I | CML, noninverting differential input for CH2. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 Device side. |
Device_TX1– | 11 | O | CML, inverting differential output for CH1. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Device side. |
Device_TX1+ | 10 | O | CML, noninverting differential output for CH1. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Device side. |
Host_TX2– | 22 | O | CML, inverting differential output for CH2. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Host side. |
Host_TX2+ | 23 | O | CML, noninverting differential output for CH2. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Host side. |
DEVICE CONTROL PINS | |||
EN_RXD | 17 | I | LVCMOS, sets device operation modes per Table 4; internally pulled to VCC. |
NC | 1, 2, 6, 12, 18, 24 | — | Pads are not internally connected. |
EQ CONTROL PINS(2) | |||
DE1, DE2 | 15, 4 | I | LVCMOS, selects de-emphasis settings for CH1 and CH2 per Table 4; internally tied to VCC/2. |
EQ1, EQ2 | 14, 5 | I | LVCMOS, selects equalization settings for CH1 and CH2 per Table 4; internally tied to VCC/2. |
OS1, OS2 | 16, NC(3) | I | LVCMOS, selects output amplitude for CH1 and CH2 per Table 4; internally tied to VCC/2. |
POWER PINS | |||
GND | 9, Thermal Pad | P | Supply ground |
VCC | 3 | P | Positive supply; must be 3.3 V ±10% |