SNx4AHC126 Quadruple Bus Buffer Gates with 3-State Outputs

1 Features

Operating range 2V to 5.5V V_CC
Low delay, 3.8 ns (typical with 5-V supply)
Latch-up performance exceeds 250mA
per JESD 17

2 Applications

3 Description

The SNx4AHC126 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.

For the high-impedance state during power up or power down, OE can be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the drive.

Package Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽²⁾	BODY SIZE (NOM)⁽³⁾
SNx4AHC126	BQA (WQFN, 14)	3mm × 2.5mm	3mm × 2.5mm
SNx4AHC126	PW (TSSOP, 14)	5mm × 6.4mm	5mm × 4.4mm

(1) For more information, see Section 11.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

(3) The body size (length × width) is a nominal value and does not include pins.

Logic Diagram (Positive Logic)

4 Pin Configuration and Functions

Figure 4-1 PW Package, 14-Pin (Top View)

Figure 4-2 BQA Package, WQFN 14-Pin (Transparent Top View)

Table 4-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
1OE	1	I	Channel 1, output enable
1A	2	I	Channel 1, A input
1Y	3	O	Channel 1, Y output
2OE	4	I	Channel 2, output enable
2A	5	I	Channel 2, A input
2Y	6	O	Channel 2, Y output
GND	7	G	Ground
3Y	8	O	Channel 3, Y output
3A	9	I	Channel 3, A input
3OE	10	I	Channel 3, OE input
4Y	11	O	Channel 4, Y output
4A	12	I	Channel 4, A input
4OE	13	I	Channel 4, OE input
V_CC	14	P	Positive supply
Thermal Pad⁽²⁾		—	Thermal pad; connect to GND or leave floating

(1) I = input, O = output, P = power, G = ground

(2) BQA package only