Home Logic & voltage translation Buffers, drivers & transceiver Noninverting buffers & drivers
Home
Logic & voltage translation
Buffers, drivers & transceiver
Noninverting buffers & drivers

SN74AHC126

ACTIVE

4-ch, 2-V to 5.5-V buffers with 3-state outputs

Order now
Data sheet

SN74AHC126

ACTIVE
Data sheet Order now

Product details

Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 8 Supply current (max) (µA) 40 IOH (max) (mA) -8 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 8 Supply current (max) (µA) 40 IOH (max) (mA) -8 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Operating range 2V to 5.5V VCC
  • Low delay, 3.8 ns (typical with 5-V supply)
  • Latch-up performance exceeds 250mAper JESD 17
  • Operating range 2V to 5.5V VCC
  • Low delay, 3.8 ns (typical with 5-V supply)
  • Latch-up performance exceeds 250mAper JESD 17

The SNx4AHC126 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.

For the high-impedance state during power up or power down, OE can be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the drive.

The SNx4AHC126 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.

For the high-impedance state during power up or power down, OE can be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the drive.
filter Find other Noninverting buffers & drivers
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device
SN74HCS125 ACTIVE Schmitt-trigger inputs quadruple bus buffer gates with 3-state outputs Larger voltage range (2V to 6V)

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 20
Type Title Date
* Data sheet SNx4AHC126 Quadruple Bus Buffer Gates with 3-State Outputs datasheet (Rev. N) PDF | HTML 27 Feb 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74AHC126 Behavioral SPICE Model

SCLM281.ZIP (7 KB) - PSpice Model
Download
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos