DATA SHEET
SN74CB3Q3125 Quadruple FET Bus Switch 2.5-V/3.3-V Low-Voltage, High-Bandwidth Bus Switch
1 Features
- High-Bandwidth Data Path (up to 500 MHz(1)(1))
- 5-V Tolerant I/Os With Device Powered Up
or Powered Down - Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range
(ron = 3 Ω Typ) - Rail-to-Rail Switching on Data I/O Ports
- 0-V to 5-V Switching With 3.3-V VCC
- 0-V to 3.3-V Switching With 2.5-V VCC
- Bidirectional Data Flow With Near-Zero Propagation Delay
- Low Input and Output Capacitance Minimizes Loading and Signal Distortion
(Cio(OFF) = 4 pF Typ) - Fast Switching Frequency (fOE = 20 MHz Max)
- Data and Control Inputs Provide Undershoot Clamp Diodes
- Low Power Consumption
(ICC = 0.3 mA Typ) - VCC Operating Range From 2.3 V to 3.6 V
- Data I/Os Support 0-V to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) - Control Inputs Can Be Driven by TTL,
5-V, or 3.3-V CMOS Outputs - Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-Distortion Signal Gating (1)
(1) For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families (SCDA008).
2 Applications
- IP Phones: Wired and Wireless
- Optical Modules
- Optical Networking: Video Over Fiber and EPON
- Private Branch Exchange (PBX)
- WiMAX and Wireless Infrastructure Equipment
3 Description
The SN74CB3Q3125 device is a high-bandwidth FET bus switch that uses a charge pump to elevate the gate voltage of the pass transistor, thus providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The SN74CB3Q3125 device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74CB3Q3125 | VQFN (14) | 3.50 mm × 3.50 mm |
| SSOP (16) | 4.90 mm × 3.90 mm | |
| TSSOP (16) | 5.00 mm × 4.40 mm | |
| TVSOP (16) | 4.40 mm × 3.60 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
Pin numbers shown are for the DGV, PW, and RGY packages.
4 Revision History
Changes from B Revision (March 2005) to C Revision
- Added Pin Functions table, ESD Ratings table, Thermal Information table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
- Deleted Ordering Information table.Go
5 Pin Configuration and Functions
DGV, PW Packages
14-Pin TVSOP, TSSOP
Top View
DBQ Package
16-Pin SSOP
Top View
RGY Package
14-Pin VQFN
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | DGV, PW, RGY | DBQ | ||
| 1OE | 1 | 2 | I | Output Enable (Active Low) |
| 1A | 2 | 3 | I/O | Channel 1A I/O 1A |
| 1B | 3 | 4 | I/O | Channel 1B I/O 1B |
| 2OE | 4 | 5 | I | Output Enable (Active Low) |
| 2A | 5 | 6 | I/O | Channel 2A I/O 2A |
| 2B | 6 | 7 | I/O | Channel 2B I/O 2B |
| GND | 7 | 8 | — | Ground |
| 3B | 8 | 10 | I/O | Channel 3B I/O 3B |
| 3A | 9 | 11 | I/O | Channel 3A I/O 3B |
| 3OE | 10 | 12 | I | Output Enable (Active Low) |
| 4B | 11 | 13 | I/O | Channel 4B I/O 4B |
| 4A | 12 | 14 | I/O | Channel 4A I/O 4B |
| 4OE | 13 | 15 | I | Output Enable (Active Low) |
| NC | — | 1, 9 | — | No Connect |
| VCC | 14 | 16 | — | Power |
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VCC | Supply voltage | –0.5 | 4.6 | V | |
| VIN | Control input voltage(2)(3) | –0.5 | 7 | V | |
| VI/O | Switch I/O voltage(2)(3)(4) | –0.5 | 7 | V | |
| II/K | Control input clamp current | VIN < 0 | –50 | mA | |
| II/OK | I/O port clamp current | VI/O < 0 | –50 | mA | |
| IIO | ON-state switch current(5) | ±64 | mA | ||
| Continuous current through VCC or GND | ±100 | mA | |||
| TJ | Junction temperature | 150 | °C | ||
| Tstg | Storage temperature | –65 | 150 | ||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O.
(5) II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | +2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | +1000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VCC | Supply voltage | 2.3 | 3.6 | V | |
| VIH | High-level control input voltage | VCC = 2.3 V to 2.7 V | 1.7 | 5.5 | V |
| VCC = 2.7 V to 3.6 V | 2 | 5.5 | |||
| VIL | Low-level control input voltage | VCC = 2.3 V to 2.7 V | 0 | 0.7 | V |
| VCC = 2.7 V to 3.6 V | 0 | 0.8 | |||
| VI/O | Data input and output voltage | 0 | 5.5 | V | |
| TA | Operating free-air temperature | –40 | 85 | °C | |
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
| THERMAL METRIC(1) | SN74CB3Q3257 | UNIT | ||||
|---|---|---|---|---|---|---|
| DBQ (SSOP) | DGV (TVSOP) | PW (TSSOP) | RGY (VQFN) | |||
| 16 PINS | 14 PINS | 14 PINS | 14 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 90 | 127 | 113 | 47 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)(1)| PARAMETER | TEST CONDITIONS | MIN | TYP(2) | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| VIK | VCC = 3.6 V, | II = –18 mA | –1.8 | V | ||||
| IIN | Control inputs | VCC = 3.6 V, | VIN = 0 to 5.5 V | ±1 | µA | |||
| IOZ(3) | VCC = 3.6 V, | VO = 0 to 5.5 V, VI = 0, |
Switch OFF, VIN = VCC or GND |
±1 | µA | |||
| Ioff | VCC = 0, | VO = 0 to 5.5 V, | VI = 0 | 1 | µA | |||
| ICC | VCC = 3.6 V, | II/O = 0, Switch ON or OFF, |
VIN = VCC or GND | 0.3 | 1 | mA | ||
| ΔICC(4) | Control inputs | VCC = 3.6 V, | One input at 3 V, | Other inputs at VCC or GND | 30 | µA | ||
| ICCD(5) | Per control input |
VCC = 3.6 V, | A and B ports open, | 0.04 | 0.2 | mA/ MHz |
||
| Control input switching at 50% duty cycle | ||||||||
| Cin | Control inputs | VCC = 3.3 V, | VIN = 5.5 V, 3.3 V, or 0 | 2.5 | 3.5 | pF | ||
| Cio(OFF) | VCC = 3.3 V, | Switch OFF, VIN = VCC or GND, |
VI/O = 5.5 V, 3.3 V, or 0 | 4 | 5 | pF | ||
| Cio(ON) | VCC = 3.3 V, | Switch ON, VIN = VCC or GND, |
VI/O = 5.5 V, 3.3 V, or 0 | 8 | 10 | pF | ||
| ron(6) | VCC = 2.3 V, TYP at VCC = 2.5 V |
VI = 0, | IO = 30 mA | 4 | 8 | Ω | ||
| VI = 1.7 V, | IO = –15 mA | 4 | 9 | |||||
| VCC = 3 V | VI = 0, | IO = 30 mA | 4 | 6 | ||||
| VI = 2.4 V, | IO = –15 mA | 4 | 8 | |||||
(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2).
(6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)| PARAMETER | FROM (INPUT) |
TO (OUTPUT) |
VCC = 2.5 V ± 0.2 V | VCC = 3.3 V ± 0.3 V | UNIT | ||
|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | ||||
| fOE(1) | OE | A or B | 10 | 20 | MHz | ||
| tpd(2) | A or B | B or A | 0.12 | 0.2 | ns | ||
| ten | OE | A or B | 1.5 | 6.7 | 1.5 | 6.6 | ns |
| tdis | OE | A or B | 1 | 4.6 | 1 | 5.3 | ns |
(1) Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0)
(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
6.7 Typical Characteristics
At TA = 25°C and VCC = 3.3 V, unless otherwise noted.
| IO = –15 mA |
| A and B Ports Open |
7 Parameter Measurement Information
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
