SCES222Q April   1999  – June 2017 SN74LVC1G86

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics, CL = 15 pF
    7. 6.7 Switching Characteristics, CL = 30 pF or 50 pF
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-voltage Tolerant Inputs
    4. 8.4 Function Table
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
  • DCK|5
  • DRL|5
  • YZP|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
  • Qualified from –40°C to +125°C
  • Supports 5-V VCC Operation
  • Inputs Are Over Voltage Tolerant up to 5.5 V
  • Supports Down Translation to VCC
  • Maximum tpd of 4 ns at 3.3 V and 15-pF load
  • Low Power Consumption, 10-µA Maximum ICC At 85°C
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode, and Back-Drive Protection
  • Available in the Texas Instruments
    NanoFree™ Package
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

2 Applications

  • Wireless Headsets
  • Motor Drives and Controls
  • TVs
  • Set-Top Boxes
  • Audio

3 Description

The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum tpd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1G86DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74LVC1G86DCK SC70 (5) 2.00 mm × 1.25 mm
SN74LVC1G86DRL SOT (5) 1.60 mm × 1.20 mm
SN74LVC1G86YZP DSBGA (5) 1.44 mm × 0.94 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

SN74LVC1G86 ces222_ls.gif
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.
These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be shown at any two ports.