OEM or retail head units where feature densities and system configurations require high efficiency in the audio power amplifier.
The TAS5404-Q1 device is a four-channel class-D audio amplifier designed for use in automotive head units. The TAS5404-Q1 device provides four channels at 20 W continuously into 4 Ω at less than 1% THD+N from a 14.4-Vdc supply when used with the application circuit. The input is configured as an analog single-ended interface. The patented PWM topology of the device provides dramatic improvements in efficiency and audio performance over traditional linear amplifier solutions. The improvement in efficiency and audio performance reduces the power dissipated by the amplifier by a factor of ten under typical music playback conditions. The device incorporates all the required functions required by the OEM application. The built-in load diagnostic functions for detecting and diagnosing disconnected speakers help reduce test time during the manufacturing process.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TAS5404-Q1 | HTQFP (64) | 14.00 mm × 14.00 mm |
Changes from * Revision (August 2015) to A Revision
PART NUMBER | MINIMUM POWER SUPPLY VOLTAGE | MAXIMUM POWER SUPPLY VOLTAGE |
---|---|---|
TAS5404-Q1 | 5.6 VDC | 18 VDC |
TAS5414C-Q1 | 6 VDC | 24 VDC |
NAME | PIN | TYPE(1) | DESCRIPTION |
---|---|---|---|
A_BYP | 11 | PBY | Bypass pin for the AVDD analog regulator |
CLIP_OTW | 6 | DO | Reports CLIP, OTW, or both. Also reports tweeter detection during tweeter mode. Open-drain |
CP | 41 | CP | Top of main storage capacitor for charge pump (bottom goes to PVDD) |
CPC_BOT | 40 | CP | Bottom of flying capacitor for charge pump |
CPC_TOP | 42 | CP | Top of flying capacitor for charge pump |
D_BYP | 5 | PBY | Bypass pin for DVDD regulator output |
FAULT | 1 | DO | Global fault output (open drain): UV, OV, OTSD, OCSD, DC |
GND | 3, 7, 8, 9, 12, 14, 16, 17, 21, 22, 23, 24, 25, 26, 30, 31, 32, 35, 38, 39, 43, 46, 49, 50, 51, 55, 56, 57, 58, 59, 60 | GND | Ground |
I2C_ADDR | 62 | AI | I2C address bit |
IN1_P | 13 | AI | Non-inverting analog input for channel 1 |
IN2_P | 15 | AI | Non-inverting analog input for channel 2 |
IN3_P | 19 | AI | Non-inverting analog input for channel 3 |
IN4_P | 20 | AI | Non-inverting analog input for channel 4 |
IN_M | 18 | ARTN | Signal return for the four analog channel inputs |
MUTE | 2 | AI | Gain ramp control: mute (low), play (high) |
OSC_SYNC | 61 | DI/DO | Oscillator input from master or output to slave amplifiers |
OUT1_M | 48 | PO | – polarity output for bridge 1 |
OUT1_P | 47 | PO | + polarity output for bridge 1 |
OUT2_M | 45 | PO | – polarity output for bridge 2 |
OUT2_P | 44 | PO | + polarity output for bridge 2 |
OUT3_M | 37 | PO | – polarity output for bridge 3 |
OUT3_P | 36 | PO | + polarity output for bridge 3 |
OUT4_M | 34 | PO | – polarity output for bridge 4 |
OUT4_P | 33 | PO | + polarity output for bridge 4 |
PVDD | 27, 28, 29, 52, 53, 54 | PWR | PVDD supply |
REXT | 10 | AI | Precision resistor pin to set analog reference |
SCL | 64 | DI | I2C clock input from system I2C master |
SDA | 63 | DI/DO | I2C data I/O for communication with system I2C master |
STANDBY | 4 | DI | Active-low STANDBY pin. Standby (low), power up (high) |