TPD3F303 ESD Protection and EMI Filter for SIM Card Interface
- SLVSAM5A January 2011 – April 2016 TPD3F303
  
  PRODUCTION DATA.

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DATA SHEET

TPD3F303 ESD Protection and EMI Filter for SIM Card Interface

1 Features

Bidirectional EMI Filtering and Line Termination With Integrated ESD Protection
- –3-dB Bandwidth 300 MHz
IEC 61000-4-2 Level 4 ESD Protection
- ±15-kV Contact Discharge
- ±15-kV Air Gap Discharge
DC Breakdown Voltage: 6 V (Minimum)
Low Leakage Current: 0.1 µA (Maximum)
Low Noise C-R-C Filter Topology
Integrated V_CC Clamp Eliminates the Need for External ESD Protection
Space-Saving DPV (0.5-mm Pitch), DQD Packages (0.4-mm Pitch)

2 Applications

End Equipment
- Cell Phones
- Tablets
- PDAs
- Hotspots
Interfaces
- SIM Cards

3 Description

The TPD3F303 device is a highly-integrated device that provides a three-channel Electromagnetic Interference (EMI) filter and a Transient Voltage Suppressor (TVS) based ESD protection diode array. The C-R-C based low-pass filter provides EMI protection for the data, clock, and reset lines of a SIM Card interface. Furthermore, the four-channel TVS Diode array provides IEC 61000-4-2 level 4 ESD protection for the previously mentioned signals (data, clock, reset) and the V_CC power line. The TPD3F303 contains a 47-Ω termination resistor for the clock line and 100-Ω termination resistor for both the data and reset lines. The high level of integration offered by the TPD3F303 makes the device well-suited for applications like cell phones, tablets, hotspots, and PDAs.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPD3F303	WSON (8)	1.35 mm × 1.70 mm
TPD3F303	USON (8)	1.60 mm × 2.10 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

4 Revision History

Changes from * Revision (January 2011) to A Revision

Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go

5 Pin Configuration and Functions

DQD or DPV Package

8-Pin WSON or USON

Top View

Pin Functions

PIN		TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
CLK_OUT	2	Output	Clock Input and Output signals.
CLK_IN	7	Input	Clock Input and Output signals.
DATA1_IN	8	Input	Data and Rest signals Input, Output pins. The DATA1 and DATA2 are symmetric circuits. They can be used interchangeably for either DATA or RESET pins based off board layout scheme.
DATA2_IN	6	Input
DATA1_OUT	1	Output
DATA2_OUT	3	Output
GND	GND	Ground	Ground connection for the EMI filter. It is very important to connect the device GND to the printed circuit board ground plane through Vias directly under the package.
NC	4	No Connect	Not connected to any internal circuit. Leave this pin floating.
V_CC	5	Power Clamp	ESD Clamp circuit for the V_CC pin.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
	I/O voltage tolerance	I/O pins		5.5	V
T_A	Operating free-air temperature		–40	85	°C
T_stg	Storage temperature		–55	155	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±15000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings – Surge Protection

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 contact discharge	±15000	V
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 air-gap discharge	±15000	V

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IO	Input pin voltage	0	5.5	V
T_A	Operating free-air temperature	–40	85	°C

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		TPD3F303		UNIT
		DPV (USON)	DQD (WSON)
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	90	92.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	93.4	103.3	°C/W
R_θJB	Junction-to-board thermal resistance	41.1	36	°C/W
ψ_JT	Junction-to-top characterization parameter	7.9	6.5	°C/W
ψ_JB	Junction-to-board characterization parameter	41	35.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	15.6	16.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_clamp	Clamp voltage	I_I/O = ±2 A	I/O pin to ground			±10	V
I_I	Leakage current	R_PU = Open	I/O pin to ground			0.1	µA
R_CLK	CLK series resistors			40	47	55	Ω
R_{DAT_RST}	Data/RST series resistors			85	100	115	Ω
C_Total	IO Capacitance	V_I/O = 0 V	I/O Pins to GND	16	20	24	pF
V_BR	Break-down Voltage	I_I/O = 1 mA		6			V
F_–3dB	–3-dB BW for DATA/RESET line	Z_SOURCE = 50 Ω Z_LOAD = 50 Ω			294		MHz
F_–3dB	–3-dB BW for CLK line	Z_SOURCE = 50 Ω Z_LOAD = 50 Ω			308		MHz

6.7 Typical Characteristics

V_IO = 2.5 V

Figure 1. I_IO vs Temperature

Figure 3. Frequency Response Data (0-V Bias)

T_A = 25°C

Figure 5. Capacitance vs V_BIAS

Figure 2. I_IOvs V_IO

Figure 4. Channel-to-Channel Crosstalk

7 Detailed Description

7.1 Overview

The TPD3F303 is a highly-integrated three-channel EMI filter and unidirectional TVS based protection diode array. This device can be used for a range of applications such as cell phones, tablets, hotspots, and PDAs.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Bidirectional EMI Filtering and Line Termination With Integrated ESD Protection

This device provides bidirectional EMI filtering, integrated line-termination resistors, and integrated ESD protection.

7.3.2 IEC 61000-4-2 ESD Protection

The ESD protection on all pins exceeds the IEC 61000-4-2 level 4 standard. Contact and air-gap ESD is rated at ±15 kV.

7.3.3 DC Breakdown Voltage

The DC breakdown voltage of this device is 6 V minimum.

7.3.4 Low Leakage Current

The I/O pins of this device feature a low leakage current of 0.1-µA maximum.

7.3.5 Low Noise C-R-C Filter Topology

This device has a C-R-C filter topology composed of a series resistor with two capacitors in parallel with the I/O pins. The typical resistor value for the DATA1 and DATA2 pins is 100 Ω and 45 Ω for the CLK pins. The typical capacitance on all lines is 20 pF when biased at 0 V.

7.3.6 Integrated V_CC Clamp

This device integrates an ESD clamp for the V_CC pin, which eliminates the need for additional components.

7.3.7 Space-Saving Packages

The layout of this device makes it easy to add protection to existing layouts. The packages offer flow-through routing which requires minimal changes to existing layout for addition of these devices. Additionally, the device is offered in two small space-saving packages that take up minimal footprint on the board.

7.4 Device Functional Modes

The TPD3F303 is a passive integrated circuit that triggers when voltages are above V_BR or below V_f (–0.7 V). During ESD events, voltages as high as ±15 kV (air or contact) can be directed to ground through the internal diode network. When the voltages on the protected line fall below the trigger levels of TPD3F303 (usually within 10s of nanoseconds) the device reverts to passive.