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  • TPS54327 3-A Output Single Synchronous Step-Down Switcher With Integrated FET

    • SLVSAG1C December   2010  – December 2015 TPS54327

      PRODUCTION DATA.  

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  • TPS54327 3-A Output Single Synchronous Step-Down Switcher With Integrated FET
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive ON-Time Control
      3. 7.3.3 Soft-Start and Prebiased Soft-Start
      4. 7.3.4 Current Protection
      5. 7.3.5 UVLO Protection
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Forced CCM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 VREG5 Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DDA|8
    • MPDS092F
  • DRC|10
    • MPDS117L
Thermal pad, mechanical data (Package|Pins)
  • DDA|8
    • PPTD058I
  • DRC|10
    • QFND013N
Orderable Information
  • slvsag1c_oa
  • slvsag1c_pm
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    • Full reading width
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    • Expanded reading width
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DATA SHEET

TPS54327 3-A Output Single Synchronous Step-Down Switcher With Integrated FET

1 Features

  • D-CAP2™ Mode Enables Fast Transient Response
  • Low-Output Ripple and Allows Ceramic Output Capacitor
  • Wide VIN Input Voltage Range: 4.5 V to 18 V
  • Output Voltage Range: 0.76 V to 7 V
  • Highly Efficient Integrated FETs Optimized
    for Lower Duty Cycle Applications
    – 100 mΩ (High-Side) and 70 mΩ (Low-Side)
  • High Efficiency, Less Than 10 μA at shutdown
  • High Initial Bandgap Reference Accuracy
  • Adjustable Soft Start
  • Prebiased Soft Start
  • 700-kHz Switching Frequency (fSW)
  • Cycle-By-Cycle Overcurrent Limit

2 Applications

  • Wide Range of Applications for Low Voltage System
    • Digital TV Power Supply
    • High Definition Blu-ray Disc™ Players
    • Networking Home Terminal
    • Digital Set Top Box (STB)

3 Description

The TPS54327 device is an adaptive on-time D-CAP2™ mode synchronous buck converter. TheTPS54327 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54327 uses the D-CAP2 mode control which provides a fast transient response with no external compensation components. The TPS54327 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between 0.76 V and 7 V. The device also features an adjustable soft start time. The TPS54327 is available in the 8-pin DDA package and 10-pin DRC, and is designed to operate from –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS54327 HSOP (8) 4.89 mm × 3.90 mm
VSON (10) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

TPS54327 FP_DS_12.gif

TPS54327 Transient Response

TPS54327 respons_lvsag1.gif

4 Revision History

Changes from B Revision (January 2012) to C Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Removed Ordering Information table Go

Changes from A Revision (October 2011) to B Revision

  • Removed (SWIFT™) from the data sheet titleGo
  • Added "and 10-pin DRC" to the DESCRIPTIONGo
  • Added the DRC-10 Pin package pin outGo
  • Changed the VBST(vs SW) MAX value From: 6V to 6.5V in the Abs Max Ratings tableGo
  • Changed the VBST(vs SW) MAX value From: 5.7V to 6V in the ROC tableGo
  • Changed UVLO MIn Value From: 0.19 V To: 0.17 VGo
  • Added Added a conditions statement "VIN = 12 V, TA = 25°C" to the TYPICAL CHARACTERISTICSGo
  • Changed Figure 10 title From: 1.05-V, 50-mA to 2-A LOAD TRANSIENT RESPONSE To: 1.05-V, 0-A to 3-A LOAD TRANSIENT RESPONSEGo
  • Changed Figure 12 Figure Title From: (IO = 2 A) To: (IO = 3 A)Go
  • Changed Figure 13 Figure Title From: (IO = 2 A) To: (IO = 3 A)Go
  • Added Figure 17Go

Changes from * Revision (November 2010) to A Revision

  • Changed Pin 6 (SW) Description In the Pin Functions table Go
  • Changed the VENH Min value From: 2 V To: 1.6 V in the Logic Threshold sectionGo
  • Changed Figure 4Go
  • Changed Equation 1Go

5 Pin Configuration and Functions

DDA Package
8-Pin HSOP
Top View
TPS54327 pin out_slvsAG1.gif
DRC Package
10-Pin VSON
Top View
TPS54327 PO_DRC.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME HSOP VSON
EN 1 1 I Enable input control. Active high.
VFB 2 2 I Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5 3 3 O 5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active when EN is low.
SS 4 4 O Soft-start control. An external capacitor should be connected to GND.
GND 5 5 G Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single point.
SW 6 6, 7 O Switch node connection between high-side NFET and low-side NFET.
VBST 7 8 I Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW pins. An internal diode is connected between VREG5 and VBST.
VIN 8 9, 10 P Input voltage supply pin.
PowerPAD Back side — G PowerPAD of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND.
Exposed thermal pad — Back side G Thermal pad of the package. PGND power ground return of internal low-side FET. Must be soldered to achieve appropriate dissipation.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage VIN, EN –0.3 20 V
VBST –0.3 26 V
VBST (10 ns transient) –0.3 28 V
VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5 V
SW –2 20 V
SW (10 ns transient) –3 22 V
Output voltage VREG5 –0.3 6.5 V
GND –0.3 0.3 V
Voltage from GND to thermal pad, Vdiff –0.2 0.2 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage 4.5 18 V
VI Input voltage VBST –0.1 24 V
VBST (10 ns transient) –0.1 27
VBST(vs SW) –0.1 6
SS –0.1 5.7
EN –0.1 18
VFB –0.1 5.5
SW –1.8 18
SW (10 ns transient) –3 21
GND –0.1 0.1
VO Output voltage VREG5 –0.1 5.7 V
IO Output Current IVREG5 0 10 mA
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS54327 UNIT
DDA (HSOP) DRC (VSON)
8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 42.1 43.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.9 55.4 °C/W
RθJB Junction-to-board thermal resistance 31.8 18.9 °C/W
ψJT Junction-to-top characterization parameter 5 0.7 °C/W
ψJB Junction-to-board characterization parameter 13.5 19.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 5.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVIN Operating - non-switching supply current VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V		 800 1200 μA
IVINSDN Shutdown supply current VIN current, TA = 25°C, EN = 0 V 1.8 10 μA
LOGIC THRESHOLD
VENH EN high-level input voltage EN 1.6 V
VENL EN low-level input voltage EN 0.45 V
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH VFB threshold voltage TA = 25°C, VO = 1.05 V, continuous mode 749 765 781 mV
IVFB VFB input current VFB = 0.8 V, TA = 25°C 0 ±0.1 μA
VREG5 OUTPUT
VVREG5 VREG5 output voltage TA = 25°C, 6 V < VIN < 18 V,
0 < IVREG5 < 5 mA		 5.2 5.5 5.7 V
VLN5 Line regulation 6 V < VIN < 18 V, IVREG5 = 5 mA 25 mV
VLD5 Load regulation 0 mA < IVREG5 < 5 mA 100 mV
IVREG5 Output current VIN = 6 V, VREG5 = 4 V, TA = 25°C 60 mA
MOSFET
RDS(on)h High-side switch resistance 25°C, VBST - SW = 5.5 V 100 mΩ
RDS(on)l Low-side switch resistance 25°C 70 mΩ
CURRENT LIMIT
Iocl Current limit L out = 1.5 μH(1), TA = -20ºC to 85ºC 3.5 4.2 5.7 A
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold Shutdown temperature (1) 165 °C
Hysteresis (1) 30
ON-TIME TIMER CONTROL
tON ON-time VIN = 12 V, VO = 1.05 V 150 ns
tOFF(MIN) Minimum OFF-time TA = 25°C, VFB = 0.7 V 260 310 ns
SOFT START
ISSC SS charge current VSS = 0 V 1.4 2 2.6 μA
ISSD SS discharge current VSS = 0.5 V 0.05 0.1 mA
UVLO
UVLO UVLO threshold Wakeup VREG5 voltage 3.45 3.75 4.05 V
Hysteresis VREG5 voltage 0.17 0.32 0.45
(1) Not production tested.

6.6 Typical Characteristics

VIN = 12 V, TA = 25°C (unless otherwise noted)
TPS54327 fig 1.gif
Figure 1. VIN Current vs Junction Temperature
TPS54327 cur_vi_lvsag1.gif
Figure 3. EN Current vs EN Voltage
TPS54327 fs_vi_lvsag1.gif
Figure 5. Switching Frequency vs Input Voltage
TPS54327 fig 2.gif
Figure 2. VIN Shutdown Current vs Junction Temperature
TPS54327 Fig_8.gif
Figure 4. Efficiency vs Output Current
TPS54327 fs_io_lvsag1.gif
Figure 6. Switching Frequency vs Output Current

 
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