The TPS548A20 is a small-sized, synchronous buck converter with an adaptive on-time D-CAP3 control mode. The device offers ease-of-use and low bill-of-material count for space-conscious power systems.
This device features high-performance integrated MOSFETs, accurate 0.6-V reference, and an integrated boost switch. Competitive features include very-low external-component count, fast load-transient response, auto-skip mode operation, internal soft-start control, and no requirement for compensation.
A forced continuous conduction mode helps meet tight voltage regulation accuracy requirements for performance DSPs and FPGAs. The TPS548A20 is available in a 28-pin VQFN-CLIP package and is specified from –40°C to 125°C ambient temperature.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS548A20 | VQFN-CLIP (28) | 4.50 mm x 3.50 mm |
Changes from * Revision (October 2015) to A Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 3 | I | The enable pin turns on the DC-DC switching converter. |
FB | 23 | I | VOUT feedback input. Connect this pin to a resistor divider between the VOUT pin and GND. |
GND | 22 | G | This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND plane with a short trace (For example, connect this pin to the thermal pad with a single trace and connect the thermal pad to PGND pins and PGND plane). |
GND1 | 27 | G | Connect this pin to ground. GND1 is the input of unused internal circuitry and must connect to ground. |
GND2 | 28 | ||
MODE | 21 | I | The MODE pin sets the forced continuous-conduction mode (FCCM) or auto-skip mode operation. It also selects the ramp coefficient of D-CAP3 mode. |
NC | 5 | — | Not connected. These pins are floating internally. |
18 | |||
26 | |||
PGND | 10 | G | These ground pins are connected to the return of the internal low-side MOSFET. |
11 | |||
12 | |||
13 | |||
14 | |||
PGOOD | 2 | O | Open-drain power-good status signal which provides startup delay after the FB voltage falls within the specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within 2 µs. |
RF | 1 | I | |
SW | 6 | I/O | SW is the output switching terminal of the power converter. Connect this pin to the output inductor. |
7 | |||
8 | |||
9 | |||
TRIP | 25 | I/O | TRIP is the OCL detection threshold setting pin. ITRIP = 10 µA at TA = 25°C, 3000 ppm/°C current is sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section for detailed OCP setting. |
VBST | 4 | P | VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch. |
VDD | 19 | P | Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V. |
VIN | 15 | P | VIN is the conversion power-supply input pins. |
16 | |||
17 | |||
VREG | 20 | O | VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver. |
VO | 24 | I | VOUT voltage input to the controller. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Input voltage range(2) | EN | –0.3 | 7.7 | V | |
SW | DC | –3 | 25 | ||
Transient < 10 ns | –5 | 27 | |||
VBST | –0.3 | 31 | |||
VBST(3) | –0.3 | 6 | |||
VBST when transient < 10 ns | 33 | ||||
VDD | –0.3 | 28 | |||
VIN | –0.3 | 25 | |||
FB, MODE, VO | –0.3 | 6 | |||
Output voltage range | PGOOD | –0.3 | 7.7 | V | |
TRIP, VREG | –0.3 | 6 | |||
Junction temperature, TJ | –40 | 150 | °C | ||
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Input voltage range | EN | –0.1 | 7 | V | |
SW | –3 | 20 | |||
VBST | –0.1 | 25.5 | |||
VBST(1) | –0.1 | 5.5 | |||
VDD | 4.5 | 25 | |||
VIN | 1.5 | 20 | |||
FB, MODE, VO | –0.1 | 5.5 | |||
Output voltage range | PGOOD | –0.1 | 7 | V | |
TRIP, VREG | –0.1 | 5.5 | |||
Ambient temperature, TA | –40 | 125 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||
IVDD | VDD bias current | TA = 25°C, No load Power conversion enabled (no switching) |
1350 | 1850 | µA | |
IVDDSTBY | VDD standby current | TA = 25°C, No load Power conversion disabled |
850 | 1150 | µA | |
IVIN(leak) | VIN leakage current | TA = 25°C, VEN = 0 V | 0.5 | µA | ||
VREF OUTPUT | ||||||
VVREF | Reference voltage | FB w/r/t GND, TA = 25°C | 597 | 600 | 603 | mV |
VVREFTOL | Reference voltage tolerance | FB w/r/t GND, -40°C ≤ TJ ≤ 85°C | –0.5 | 0.5 | % | |
FB w/r/t GND, –40°C ≤ TJ ≤ 125°C | –1.0 | 1.0 | ||||
OUTPUT VOLTAGE | ||||||
IFB | FB input current | VFB = 600 mV | 50 | 100 | nA | |
IVODIS | VO discharge current | VVO = 0.5 V, Power Conversion Disabled | 6 | uA | ||
SMPS FREQUENCY | ||||||
fSW | VO switching frequency | VIN = 12 V, VVO = 3.3 V, RRF<0.041 | 250 | kHz | ||
VIN = 12 V, VVO = 3.3 V, RRF=0.096 | 300 | |||||
VIN = 12 V, VVO = 3.3 V, RRF=0.16 | 400 | |||||
VIN = 12 V, VVO = 3.3 V, RRF=0.229 | 500 | |||||
VIN = 12 V, VVO = 3.3 V, RRF=0.297 | 600 | |||||
VIN = 12 V, VVO = 3.3 V, RRF=0.375 | 750 | |||||
VIN = 12 V, VVO = 3.3 V, RRF=0.461 | 850 | |||||
VIN = 12 V, VVO = 3.3 V, RRF>0.557 | 1000 | |||||
tON(min) | Minimum on-time | TA = 25°C(1) | 60 | ns | ||
tOFF(min) | Minimum off-time | TA = 25°C | 175 | 240 | 310 | ns |
INTERNAL BOOTSTRAP SW | ||||||
VF | Forward Voltage | VVREG–VBST, TA = 25°C, IF = 10 mA | 0.15 | 0.25 | V | |
IVBST | VBST leakage current | TA = 25°C, VVBST = 33 V, VSW = 28 V | 0.01 | 1.5 | µA | |
LOGIC THRESHOLD | ||||||
VENH | EN enable threshold voltage | 1.3 | 1.4 | 1.5 | V | |
VENL | EN disable threshold voltage | 1.1 | 1.2 | 1.3 | V | |
VENHYST | EN hysteresis voltage | 0.22 | V | |||
VENLEAK | EN input leakage current | –1 | 0 | 1 | µA | |
SOFT-START | ||||||
tSS | Soft-start time | 4 | ms | |||
POWERGOOD COMPARATOR | ||||||
VPGTH | PGOOD threshold | PGOOD in from higher | 104 | 108 | 111 | % |
PGOOD in from lower | 89 | 92 | 96 | % | ||
PGOOD out to higher | 113 | 116 | 120 | % | ||
PGOOD out to lower | 80 | 84 | 87 | % | ||
tPGDLY | PGOOD delay time | Delay for PGOOD going in | 0.8 | 1.0 | 1.2 | ms |
Delay for PGOOD coming out | 2 | µs | ||||
IPG | PGOOD sink current | VPGOOD = 0.5 V | 4 | 6 | mA | |
IPGLK | PGOOD leakage current | VPGOOD = 5.0 V | –1 | 0 | 1 | µA |
POWER-ON DELAY | ||||||
tPODLY | Power-on delay time | Delay from enable to switching | 1.124 | ms | ||
CURRENT DETECTION | ||||||
IOCL | Current limit threshold, valley | RTRIP = 49 kΩ | 11.5 | 15.0 | 17.5 | A |
RTRIP = 28 kΩ | 6.5 | 8 | 11 | |||
IOCLN | Negative current limit threshold, valley | RTRIP = 49 kΩ | -18.0 | –14.9 | -10.5 | A |
RTRIP = 28 kΩ | -11.5 | -8.0 | -6.0 | |||
VZC | Zero cross detection offset | 0 | mV | |||
PROTECTIONS | ||||||
VVREGUVLO | VREG undervoltage-lockout (UVLO) threshold voltage | Wake-up | 3.25 | 3.34 | 3.41 | V |
Shutdown | 3.00 | 3.12 | 3.19 | |||
VVDDUVLO | VDD UVLO threshold voltage | Wake-up (default) | 4.15 | 4.25 | 4.35 | V |
Shutdown | 3.95 | 4.05 | 4.15 | |||
VOVP | Overvoltage-protection (OVP) threshold voltage | OVP detect voltage | 116 | 120 | 124 | % |
tOVPDLY | OVP propagation delay | With 100-mV overdrive | 300 | ns | ||
VUVP | Undervoltage-protection (UVP) threshold voltage | UVP detect voltage | 64 | 68 | 71 | % |
tUVPDLY | UVP delay | UVP filter delay | 1 | ms | ||
THERMAL SHUTDOWN | ||||||
TSDN | Thermal shutdown threshold(1) | Shutdown temperature | 140 | °C | ||
Hysteresis | 40 | |||||
LDO VOLTAGE | ||||||
VREG | LDO output voltage | VIN = 12 V, ILOAD = 10 mA | 4.65 | 5 | 5.45 | V |
VDOVREG | LDO low droop drop-out voltage | VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C | 365 | mV | ||
ILDOMAX | LDO over-current limit | VIN = 12 V, TA = 25°C | 170 | 200 | mA | |
INTERNAL MOSFETS | ||||||
RDS(on)H | High-side MOSFET on-resistance | TA = 25°C | 9.9 | 11.4 | mΩ | |
RDS(on)L | Low-side MOSFET on-resistance | TA = 25°C | 4.3 | 4.94 | mΩ |
THERMAL METRIC(1) | TPS548A20 | UNIT | |
---|---|---|---|
RVE (VQFN-CLIP) |
|||
28 PINS | |||
θJA | Junction-to-ambient thermal resistance | 37.5 | °C/W |
θJCtop | Junction-to-case (top) thermal resistance | 34.1 | °C/W |
θJB | Junction-to-board thermal resistance | 18.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 18.1 | °C/W |
θJCbot | Junction-to-case (bottom) thermal resistance | 2.2 | °C/W |
fSW = 500 kHz | Auto-skip Mode |
VIN = 12 V |
fSW = 970 kHz | Auto-skip Mode |
VIN = 12 V |
fSW = 500 kHz | VOUT = 1.2 V |
fSW = 500 kHz | VOUT = 1.2 V |
fSW = 500 kHz | VIN = 12 V |
VOUT = 5 V |
VIN = 12 V | VOUT = 1.2 V | ||
fSW = 500 kHz | FCCM |
VIN = 12 V |
fSW = 970 kHz | FCCM |
VIN = 12 V |
fSW = 970 kHz | VOUT = 1.2 V |
fSW = 970 kHz | VOUT = 1.2 V |
fSW = 500 kHz | VIN = 12 V |
VOUT = 1 V |
fSW = 1 MHz | VIN = 12 V |
VOUT = 1.2 V | ILOAD = 0 A |
fSW = 1 MHz | VIN = 12 V |
VOUT = 1.2 V | ILOAD = 0.1 A |
fSW = 1 MHz | VIN = 12 V |
VOUT = 1.2 V | ILOAD = 8 A |
ILOAD from 0 A to 8 A | Div = 2 A/µs |
VIN = 12 V | VOUT = 1.2 V |
fSW = 1 MHz |
fSW = 1 MHz | VIN = 12 V |
VOUT = 1.2 V |
ILOAD = 0 A | VIN = 12 V |
VOUT = 1.2 V | fSW = 1 MHz |
ILOAD = 8A | VIN = 12 V |
VOUT = 1.2 V | fSW = 1 MHz |
ILOAD = 0 A | VIN = 12 V |
VOUT = 1.2 V | fSW = 1 MHz |
fSW = 1 MHz | VIN = 12 V |
VOUT = 1.2 V | ILOAD = 0 A |
fSW = 1 MHz | VIN = 12 V |
VOUT = 1.2 V | ILOAD = 0.1 A |
fSW = 1 MHz | VIN = 12 V |
VOUT = 1.2 V | ILOAD = 8 A |
ILOAD from 0 A to 8 A | Div = 2 A/µs |
VIN = 12 V | VOUT = 1.2 V |
fSW = 1 MHz |
fSW = 1 MHz | VIN = 12 V |
VOUT = 1.2 V |
ILOAD = 0 A | VIN = 12 V |
VOUT = 1.2 V | fSW = 1 MHz |
ILOAD = 8 A | VIN = 12 V |
VOUT = 1.2 V | fSW = 1 MHz |
ILOAD = 8 A | VIN = 12 V |
VOUT = 1.2 V | fSW = 1 MHz |