The TPS56528 device is an adaptive on-time
D-CAP2™ mode synchronous buck converter. The TPS56528 enables system designers to complete the suite of various end-equipment power bus regulators with a cost-effective, low component count, low standby current solution. The main control loop for the TPS56528 uses the D-CAP2™ mode control that provides a fast transient response with no external compensation components. The adaptive on-time control supports seamless transition between PWM mode at higher load conditions and advanced Eco-Mode™ operation at light loads. Advanced Eco-Mode™ allows the TPS56528 to maintain high efficiency during lighter load conditions. The TPS56528 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between 0.6 V and 7 V. The device also features a fixed 1-ms soft-start time and power good output. The TPS56528 is available in the 8-pin SO PowerPAD™ package, and designed to operate from –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS56528 | SO PowerPAD (8) | 4.89 mm × 3.90 mm |
Changes from A Revision (April 2013) to B Revision
Changes from * Revision (April 2013) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | EN | I | Enable input control. EN is active high and must be pulled up to enable the device. |
2 | VFB | I | Converter feedback input. Connect to output voltage with feedback resistor divider. |
3 | VREG5 | O | 5.5-V power supply output. A capacitor (0.47 µF typical) must be connected to GND. VREG5 is not active when EN is low. |
4 | PG | O | Open-drain power good output. |
5 | GND | — | Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single point. |
6 | SW | O | Switch node connection between high-side NFET and low-side NFET. |
7 | VBST | O | Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between VBST and SW pins. An internal diode is connected between VREG5 and VBST. |
8 | VIN | I | Input voltage supply pin. |
— | PowerPAD | — | Thermal pad of the package. This pad must be soldered to achieve appropriate dissipation and must be connected to GND. |