TPS6217x 28-V, 0.5-A Step-Down Converter With Sleep Mode
- SLVSB35C October 2012 – July 2015 TPS62175 , TPS62177
  
  PRODUCTION DATA.

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DATA SHEET

TPS6217x 28-V, 0.5-A Step-Down Converter With Sleep Mode

1 Features

DCS-Control™ Topology
Input Voltage Range 4.75 V to 28 V
Quiescent Current Typically 4.8 µA (Sleep Mode)
100% Duty Cycle Mode
Active Output Discharge
Power Good Output
Output Current of 500 mA
Output Voltage Range 1 VDC to 6 V
Switching Frequency of Typically 1 MHz
Seamless Power Save Mode Transition
Undervoltage Lockout
Short Circuit Protection
Over Temperature Protection
Available in 2-mm × 3-mm 10-pin WSON Package

2 Applications

General 12 V / 24 V Point Of Load Supply
Ultra Mobile PC, Embedded PC
Low Power Supply for Microprocessor
High Efficiency LDO Alternative
Industrial Sensors

3 Description

The TPS6217x is a high efficiency synchronous step-down DC/DC converter, based on the DCS-Control™ topology.

With a wide operating input voltage range of 4.75 V to 28 V, the device is ideally suited for systems powered from multi cell Li-Ion as well as 12 V and even higher intermediate supply rails, providing up to 500-mA output current.

The TPS6217x automatically enters power save mode at light loads, to maintain high efficiency across the whole load range. As well, it features a sleep mode to supply applications with advanced power save modes like ultra low power micro controllers. The power good output may be used for power sequencing and/or power on reset.

The device features a typical quiescent current of 22 µA in normal mode and 4.8 µA in sleep mode. In sleep mode, the efficiency at very low load currents can be increased by as much as 20%. In shutdown mode, the shutdown current is less than 2 µA and the output is actively discharged.

The TPS6217x, available in an adjustable and a fixed output voltage version, is packaged in a small 2-mm × 3-mm 10-pin WSON package.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS6217x	WSON (10)	2.00 mm × 3.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

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Typical Application Schematic

Efficiency vs Output Current

TPS62175 TPS62177 SLVSB35_pageone_efficiency.gif

4 Revision History

Changes from B Revision (January 2014) to C Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from A Revision (November 2012) to B Revision

Added to SLEEP description in TERMINAL FUNCTIONS tableGo
Changed Sleep Mode Operation sectionGo
Changed Micro Controller Power Supply section information and Figure 54Go
Changed Figure 55 Go

Changes from * Revision (October 2012) to A Revision

Added Start-up Mode to High-Side MOSFET Current Limit in ELECTRICAL CHARACTERISTICSGo
Changed Table 2 Go

5 Device Comparison Table

PART NUMBER	OUTPUT VOLTAGE	PACKAGE DESIGNATOR CODE	PACKAGE MARKING
TPS62175	Adjustable	DQC	62175
TPS62177	Fixed, 3.3 V	DQC	62177

6 Pin Configuration and Functions

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DQC Package

10-Pin WSON

Top View

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Pin Functions

PIN ⁽¹⁾		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
PGND	1	—	Power ground connection
VIN	2	I	Supply voltage for the converter
EN	3	I	Enable input (High = enabled, Low = disabled)
NC	4	—	This pin is recommended to be connected to AGND but can left be floating
FB	5	I	Voltage feedback of adjustable version. Connect resistive divider to this pin. TI recommends connecting FB to AGND for fixed voltage versions for improved thermal performance.
AGND	6	—	Analog ground connection
PG	7	O	Output power good (open drain, requires pullup resistor)
SLEEP	8	I	Sleep mode input (High = normal operation, Low = sleep mode operation). Can be operated dynamically during operation. If sleep mode is not used, connect to VOUT.
SW	9	O	Switch node, connected to the internal MOSFET switches. Connect inductor between SW and output capacitor.
VOS	10	I	Output voltage sense pin and connection for the control loop circuitry.
Exposed Thermal Pad	—	—	Must be connected to AGND and PGND. Must be soldered to achieve appropriate power dissipation and mechanical reliability.

(1) For more information about connecting pins, see Detailed Description and Application and Implementation sections.

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Pin voltage⁽²⁾	VIN	–0.3	30	V
	EN, SW	–0.3	V_IN+ 0.3
	FB, PG, VOS, SLEEP, NC	–0.3	7
Power good sink current	PG		10	mA
Temperature	Operating junction temperature, T_J	–40	125	°C
Temperature	Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) All voltages are with respect to network ground terminal.

7.2 ESD Ratings

			VALUE		UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000		V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

	MIN	MAX	UNIT
Supply voltage, V_IN	4.75	28	V
Operating free air temperature, T_A	–40	85	°C
Operating junction temperature, T_J	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS6217x	UNIT
		DQC [WSON]
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	61.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	65.5	°C/W
R_θJB	Junction-to-board thermal resistance	22.5	°C/W
ψ_JT	Junction-to-top characterization parameter	1.4	°C/W
ψ_JB	Junction-to-board characterization parameter	22.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	5.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Over free-air temperature range (T_A = –40°C to 85°C) and V_IN = 4.75 V to 28 V. Typical values at V_IN = 12 V and T_A = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	UNIT
SUPPLY
V_IN	Input voltage range				4.75		28	V
I_Q	Operating quiescent current	EN = High, SLEEP = High, I_OUT = 0 mA, device not switching				22	36	µA
I_{Q_SLEEP}	Sleep mode quiescent current	EN = High, SLEEP = Low, I_OUT = 0 mA, device not switching				4.8	10	µA
I_SD	Shutdown current	EN = Low, current into VIN pin				1.5	5	µA
V_UVLO	Undervoltage lockout threshold	Rising input voltage			4.5	4.6	4.7	V
V_UVLO	Undervoltage lockout threshold	Falling input voltage				2.9		V
T_SD	Thermal shutdown temperature	Rising junction temperature				150		°C
T_SD	Thermal shutdown hysteresis					20		°C
CONTROL (EN, PG, SLEEP)
V_H	High level input threshold voltage (EN, SLEEP)				0.9			V
V_L	Low level input threshold voltage (EN, SLEEP)						0.3	V
I_{LKG_EN}	Input leakage current (EN)	EN = V_IN				5	300	nA
I_{LKG_SLEEP}	Input leakage current (SLEEP)	V_SLEEP = 3.3 V				1.4		µA
V_{TH_PG}	Power good threshold voltage	Rising (%V_OUT)			93%	96%	99%
V_{TH_PG}	Power good threshold voltage	Falling (%V_OUT)			87%	90%	93%
V_{OL_PG}	Power good output low voltage	I_PG= –2 mA					0.3	V
I_{LKG_PG}	Input leakage current (PG)	V_PG= 5 V				5	300	nA
POWER SWITCH
R_DS(ON)	High-side MOSFET ON-resistance	V_IN≥ 6 V				850	1430	mΩ
R_DS(ON)	Low-side MOSFET ON-resistance	V_IN≥ 6 V				320	530	mΩ
I_LIMF	High-side MOSFET current limit	Normal operation			800	1000	1200	mA
I_LIMF	High-side MOSFET current limit	Start-up mode			450	525	600	mA
OUTPUT
V_OUT	Output voltage range (TPS62175)	V_IN ≥ V_OUT			1		6	V
V_REF	Internal reference voltage					0.8		V
I_{OUT_SLEEP}	Output current in sleep mode	SLEEP = Low, V_OUT = 3.3 V, L = 10 µH			15			mA
I_{LKG_FB}	Input leakage current (FB)	V_FB = 0.8 V				1	100	nA
V_OUT	Output voltage accuracy⁽¹⁾	TPS62175 (adjustable V_OUT), V_IN ≥ V_OUT +1 V	PWM mode		–1.8%		1.8%
			Power save mode, L = 10 µH	V_OUT ≥ 2.5 V, C_OUT= 22 µF	–1.8%		3%
			Power save mode, L = 10 µH	V_OUT < 2.5 V, C_OUT = 44 µF	–1.8%		3.7%
			Sleep mode, I_OUT ≤ 15 mA	C_OUT = 22 µF, L = 10 µH	–1.6%		2.9%
		TPS62177 (3.3 V fixed V_OUT)	PWM mode		–2%		2%
			Power save mode,	C_OUT = 22 µF, L = 10 µH	–2%		2.9%
			Sleep mode, I_OUT ≤ 15 mA	C_OUT = 22 µF, L = 10 µH	–1.6%		2.7%
	Output discharge resistance	EN = Low				175		Ω
	Load regulation	V_OUT = 3.3 V, PWM mode operation				0.02		%/A
	Line regulation	V_OUT = 3.3 V, I_OUT= 500 mA, PWM mode operation				0.015		%/V

(1) The output voltage accuracy in Power Save and Sleep Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple (see Application and Implementation section).

7.6 Typical Characteristics

Figure 1. Quiescent Current

Figure 3. Shutdown Current

Figure 5. Low-Side Switch

Figure 2. Quiescent Current (Sleep Mode)

Figure 4. High-Side Switch