TPS65910x Integrated Power-Management Unit Top Specification
- SWCS046U March 2010 – October 2014 TPS65910
  
  PRODUCTION DATA.

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DATA SHEET

TPS65910x Integrated Power-Management Unit Top Specification

1 Device Overview

1.1 Features

Embedded Power Controller
Two Efficient Step-Down DC-DC Converters for Processor Cores
One Efficient Step-Down DC-DC Converter for I/O Power
One Efficient Step-Up 5-V DC-DC Converter
SmartReflex™ Compliant Dynamic Voltage Management for Processor Cores
8 LDO Voltage Regulators and One Real-Time Clock (RTC) LDO (Internal Purpose)
One High-Speed I²C Interface for General-Purpose Control Commands (CTL-I²C)
One High-Speed I²C Interface for SmartReflex Class 3 Control and Command (SR-I²C)
Two Enable Signals Multiplexed with SR-I²C, Configurable to Control any Supply State and Processor Cores Supply Voltage
Thermal Shutdown Protection and Hot-Die Detection
An RTC Resource With:
- Oscillator for 32.768-kHz Crystal or 32-kHz Built-in RC Oscillator
- Date, Time, and Calendar
- Alarm Capability
One Configurable GPIO
DC-DC Switching Synchronization Through Internal or External 3-MHz Clock

1.2 Applications

Portable and Handheld Systems
Industrial Systems

1.3 Description

The TPS65910 device is an integrated power-management IC available in 48-QFN package and dedicated to applications powered by one Li-Ion or Li-Ion polymer battery cell or 3-series Ni-MH cells, or by a 5-V input; it requires multiple power rails. The device provides three step-down converters, one step-up converter, and eight LDOs and is designed to support the specific power requirements of OMAP-based applications.

Two of the step-down converters provide power for dual processor cores and are controllable by a dedicated class-3 SmartReflex interface for optimum power savings. The third converter provides power for the I/Os and memory in the system.

The device includes eight general-purpose LDOs providing a wide range of voltage and current capabilities. The LDOs are fully controllable by the I²C interface. The use of the LDOs is flexible; they are intended to be used as follows: Two LDOs are designated to power the PLL and video DAC supply rails on the OMAP-based processors, four general-purpose auxiliary LDOs are available to provide power to other devices in the system, and two LDOs are provided to power DDR memory supplies in applications requiring these memories.

In addition to the power resources, the device contains an embedded power controller (EPC) to manage the power sequencing requirements of the OMAP systems and an RTC.

Table 1-1 Device Information⁽¹⁾

PART NUMBER	PACKAGE (PIN)	BODY SIZE
TPS65910	PVQFN (48)	6.00 mm × 6.00 mm

(1) For more information, see Section 8, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the top-level diagram of the device.

Figure 1-1 48-QFN Top-Level Diagram

2 Revision History

VERSION	DATE	NOTES
*	03/2010	See ⁽¹⁾
A	05/2010	See ⁽²⁾
B	06/2010	See ⁽³⁾
C	06/2010	See ⁽⁴⁾
D	11/2010	See ⁽⁵⁾
E	01/2011	See ⁽⁶⁾
F	01/2011	See ⁽⁷⁾
G	05/2011	See ⁽⁸⁾
H	06/2011	See ⁽⁹⁾
I	07/2011	See ⁽¹⁰⁾
J	10/2011	See ⁽¹¹⁾
K	10/2011	See ⁽¹²⁾
L	01/2012	See ⁽¹³⁾
M	03/2012	See ⁽¹⁴⁾
N	04/2012	See ⁽¹⁵⁾
O	06/2012	See ⁽¹⁶⁾
P	09/2012	See ⁽¹⁷⁾
Q	09/2012	See ⁽¹⁸⁾
R	02/2013	See ⁽¹⁹⁾
S	08/2013	See ⁽²⁰⁾
T	09/2013	See ⁽²¹⁾
U	10/2014	See ⁽²²⁾

(1) Initial release

(2) SWCS046A: Updated register tables VMMC_REG and VDAC_REG. Added register table VPLL_REG

(3) SWCS046B: Updated Absolute Maximum Ratings, Recommended Operating Conditions, I/O Pullup and Pulldown Characteristics, Digital I/Os Voltage Electrical Characteristics, Power Consumption, Power References and Thresholds, Thermal Monitoring and Shutdown, 32-kHz RTC Clock, VRTC LDO, VIO SMPS, VDD1 SMPS, VDD2 SMPS, VDD3 SMPS, Switch-On/-Off Sequences and Timing

(4) SWCS046C: Associate parts; no change.

(5) SWCS046D: Updated Recommended Operating Conditions - Backup Battery, I/O Pullup and Pulldown Characteristics, Backup Battery Charger. Update Rated output current, PMOS current limit (High-Side), NMOS current limit (Low-Side), and Conversion Efficiency for VIO SMPS, VDD1/VDD2/VDD3 SMPS and VDIG1/VDIG2 LDO. Update Input Voltage for VIO/VDD1/VDD2 SMPS. Update DC and Transient Load and Line Regulation and Internal Resistance for VDIG1/VDIG2 LDO, VAUX33/VMMC LDO, VAUX1,VAUX2, LDO, and VDAC/VPLL LDO. Update DC Load Regulation for VAUX3/VMMC/VDAC. Update Power Control Timing. Add Device SLEEP State Control. Add SMPS Switching Synchronization. Update VIO_REG, VDD1_REG, and VDD2_REG.

(6) SWCS046E: Manually added Thermal Pad Mechanical Data.

(7) SWCS046F: UpdatedTable 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.

(8) SWCS046G: Updated Section 6.11, Section 5.3, Section 5.6, and Section 6.3.3.6.

(9) SWCS046H: Updated Table 6-29, PUADEN_REG, Table 6-61, RESERVED, and Table 6-62, RESERVED.

(10) SWCS046I: Updated DC Output voltage V_OUT in Section 5.20.

(11) SWCS046J: UpdatedTable 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.

(12) SWCS046K: UpdateTable 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS - Add AM335x.

(13) SWCS046L: Updated Table 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS - Add AM335x with DDR2 and AM335x with DDR3.

(14) SWCS046M: Updated Section 6.3.1, - Update Device Sleep enable conditions control information.

(15) SWCS046N:

Section 5.14 - Updated PMOS current limit (high side) conditions
Table 6-63 - Updated INT_STS_REG register - VMBHI_IT description
Updated Input voltage: Section 5.18

(16) SWCS046O: Updated Table 5-5, Power Control Timing Characteristics

Replace unit of µs for t_dbPWRONF by ms

(17) SWCS046P: Updated Table 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS -

Add AM335x with DDR3 - TPS65910A31A1RSL
Add Rockchip - RK30xx

(18) SWCS046Q: Updated Table 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS -

Refer to SWCU093 document: Updated document reference from TBD to SWCU093

(19) SWCS046R: Updated Section 5.13, VRTC LDO - Changed Input Voltage - Back-up mode - Max from 3V to 5.5V.

(20) SWCS046S: Updated Section 5.20, VAUX1 AND VAUX2 LDO - Changed VAUX2 - Rated Output Current I_OUTmax - On mode from 150 mA to 300 mA

(21) SWCS046T: Updated

Table 6-23, RTC_Reset_Status_Reg, Changed Reserved bits to 7:1 and changed RESET_STATUS's reset value to 0x0.
Table 6-34, VDD1_OP_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.
Table 6-35, VDD1_SR_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.
Table 6-37, VDD2_OP_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.
Table 6-38, VDD2_SR_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.

(22) SWCS046U: Updated data sheet to latest TI standards

Updated Section 1.2, Applications
Added Table 1-1, Device Information
Moved Section 4, Terminal Configuration and Functions
Moved appropriate data to Section 5.2
Added Section 5.4, Thermal Resistance Characteristics for RSL Package

3 Device Comparison

Table 3-1 Supported Processors and Corresponding Part Numbers

Compatible Processor⁽¹⁾	Part Number⁽¹⁾
TI processor - AM335x with DDR2	TPS65910AA1RSL
TI processor - AM335x with DDR3	TPS65910A3A1RSL
TI processor - AM335x with DDR3⁽²⁾	TPS65910A31A1RSL
TI processors - AM1705/07, AM1806/08, AM3505/17, AM3703/15, DM3730/25, OMAP-L137/38, OMAP3503/15/25/30, TMS320C6742/6/8	TPS65910A1RSL
Samsung - S5PV210, S5PC110	TPS659101A1RSL
Rockchip - RK29xx, RK30xx	TPS659102A1RSL
Samsung - S5PC100	TPS659103A1RSL
Samsung - S5P6440	TPS659104A1RSL
TI processors - DM643x, DM644x	TPS659105A1RSL
Reserved	TPS659106A1RSL
Freescale - i.MX27, Freescale - i.MX35	TPS659107A1RSL
Freescale - i.MX508	TPS659108A1RSL
Freescale - i.MX51	TPS659109A1RSL

(1) The RSL package is available in tape and reel. See for details for corresponding part numbers, quantities and ordering information.

(2) Refer to SWCU093, TPS65910Ax User's Guide For AM335x Processors

4 Terminal Configuration and Functions

Figure 4-1 shows the pin assignments.

Figure 4-1 48-QFN Top-View Pin Assignment

4.1 Signal Descriptions

Table 4-1 Signal Descriptions

NAME	QFN PIN	SUPPLIES	TYPE	I/O	DESCRIPTION	PU/PD
VDDIO		VDDIO/DGND	Power	I	Digital I/Os supply	No
SDA_SDI		VDDIO/DGND	Digital	I/O	I²C bidirectional data signal/serial peripheral interface data input (multiplexed)	External PU
SCL_SCK		VDDIO/DGND	Digital	I/O	I²C bidirectional clock signal/serial peripheral interface Clock Input (multiplexed)	External PU
SDASR_EN2		VDDIO/DGND	Digital	I/O	I²C SmartReflex bidirectional data signal/enable of supplies (multiplexed)	External PU
SCLSR_EN1		VDDIO/DGND	Digital	I/O	I²C SmartReflex bidirectional clock signal/enable of supplies (multiplexed)	External PU
SLEEP		VDDIO/DGND	Digital	I	Active-sleep state transition control signal	Programmable PD (default active)
GPIO_CKSYNC		VDDIO/DGND	Digital	I/O	Configurable general-purpose I/O or DC-DCs synchronization clock input signal	Programmable PD (default active)
PWRHOLD		VRTC/DGND	Digital	I	Switch-on/-off control signal	Programmable PD (default active)
PWRON		VBAT/DGND	Digital	I	External switch-on control (ON button)	Programmable PU (default active)
NRESPWRON		VDDIO/DGND	Digital	O	Power off reset	PD active during device OFF state
INT1		VDDIO/DGND	Digital	O	Interrupt flag	No
BOOT0		VRTC/DGND	Digital	I	Power-up sequence selection	Programmable PD (default active)
BOOT1		VRTC/DGND	Digital	I	Power-up sequence selection	Programmable PD (default active)
CLK32KOUT		VDDIO/DGND	Digital	O	32-kHz clock output	PD disable in ACTIVE or SLEEP state
OSC32KIN		VRTC/REFGND	Analog	I	32-kHz crystal oscillator	No
OSC32KOUT		VRTC/REFGND	Analog	I	32-kHz crystal oscillator	No
VREF		VCC7/REFGND	Analog	O	Bandgap voltage	No
REFGND		REFGND	Analog	I/O	Reference ground	No
TESTV		VCC7/AGND	Analog	O	Analog test output (DFT)	No
VBACKUP		VBACKUP/AGND	Power	I	Backup battery input (short to VCC5 if not used)	No
VCC1		VCC1/GND1	Power	I	VDD1 DC-DC power input	No
GND1		VCC1/GND1	Power	I/O	VDD1 DC-DC power ground	No
SW1		VCC1/GND1	Power	O	VDD1 DC-DC switched output	No
VFB1		VCC7/AGND	Analog	I	VDD1 feedback voltage	PD
VCC2		VCC2/GND2	Power	I	VDD2 DC-DC power input	No
GND2		VCC2/GND2	Power	I/O	VDD2 DC-DC power ground	No
SW2		VCC2/GND2	Power	O	VDD2 DC-DC switched output	No
VFB2		VCC4/AGND2	Analog	I	VDD2 DC-DC feedback voltage	PD
VCCIO		VCCIO/GNDIO	Power	I	VIO DC-DC power input	No
GNDIO		VCCIO/GNDIO	Power	I/O	VIO DC-DC power ground	No
SWIO		VCCIO/GNDIO	Power	O	VIO DC-DC switched output	No
VFBIO		VCC7/AGND	Analog	I	VIO feedback voltage	PD
VCC3		VCC3/AGND2	Power	I	VMMC VAUX33 power input	No
VMMC		VCC3/REFGND	Power	O	LDO regulator output	PD
VAUX33		VCC3/REFGND	Power	O	LDO regulator output, VDD3 internal regulated supply	PD
VCC4		VCC4/AGND2	Power	I	VAUX1, VAUX2 power input	No
VAUX1		VCC4/REFGND	Power	O	LDO regulator output	PD
VAUX2		VCC4/REFGND	Power	O	LDO regulator output	PD
VCC5		VCC5/AGND	Power	I	VDAC, VPLL power input	No
VDAC		VCC5/REFGND	Power	O	LDO regulator output	PD
VPLL		VCC5/REFGND	Power	O	LDO regulator output	PD
VRTC		VCC7/REFGND	Power	O	LDO regulator output	PD
VCC6		VCC6/AGND2	Power	I	VDIG1, VDIG2 power input	No
VDIG1		VCC6/REFGND	Power	O	LDO regulator output	No
VDIG2		VCC6/REFGND	Power	O	LDO regulator output	No
VCC7		VCC7/REFGND	Power	I	VRTC power input, VDD3 internal and analog references supply	No
VFB3		VCC7/AGND	Analog	I	VDD3 feedback voltage	No
SW3		VCC7/GND3	Power	O	VDD3 DC-DC switched output	No
GND3	Power PAD	AGND	Power	I/O	VDD3 DC-DC power ground	No
AGND	Power PAD	AGND	Power	I/O	Analog ground	No
AGND2	Power PAD	AGND	Power	I/O	Analog ground	No
DGND	Power PAD	DGND	Power	I/O	Digital ground	No

5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5, VCC6, VCC7	–0.3	7	V
Voltage range on pins/balls VDDIO	–0.3	3.6	V
Voltage range on pins/balls OSC32KIN, OSC32KOUT, BOOT1, BOOT0	–0.3	VRTC_MAX + 0.3	V
Voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1, SLEEP, INT1, CLK32KOUT, NRESPWRON	–0.3	VDDIO_MAX + 0.3	V
Voltage range on pins/balls PWRON	–0.3	7	V
Voltage range on pins/balls PWRHOLD⁽³⁾ GPIO_CKSYNC⁽⁴⁾	–0.3	7	V
Peak output current on all other terminals than power resources	–5	5	mA

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) I/O supplied from VDDIO but which can be driven from to a VBAT voltage level

(4) I/O supplied from VRTC but can be driven to a VBAT voltage level

5.2 Handling Ratings

				MIN	MAX	UNIT
T_stg	Storage temperature range			–45	150	°C
V_ESD	Electrostatic discharge (ESD) performance:	Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾		–2	2	kV
V_ESD	Electrostatic discharge (ESD) performance:	Charged Device Model (CDM), per JESD22-C101⁽²⁾	All pins	–500	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
Note 1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that VCC2 and VCC4 can be higher than VCC7.
Note 2: VCC2 and VCC4 must be connected together (to the same voltage).
Note 3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.

PARAMETER	TEST CONDITIONS	MIN	NOM	MAX	UNIT
V_CC: Input voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5, VCC7		2.7	3.6	5.5	V
V_CCP: Input voltage range on pins/balls VCC6		1.7	3.6	5.5	V
Input voltage range on pins/balls VDDIO		1.65	1.8/3.3	3.45	V
Input voltage range on pins/balls PWRON		0	3.6	5.5	V
Input voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1, SLEEP		1.65	VDDIO	3.45	V
Input voltage range on pins/balls PWRHOLD, GPIO_CKSYNC		1.65	VDDIO	5.5	V
Input voltage range on balls BOOT1, BOOT0, OSC32KIN		1.65	VRTC	1.95	V
Operating free-air temperature, T_A		–40	27	85	°C
Junction temperature, T_J		–40	27	125	°C
Storage temperature range		–65	27	150	°C
Lead temperature (soldering, 10 s)			260		°C
Power References
VREF filtering capacitor C_O(VREF)	Connected from VREF to REFGND		100		nF
VDD1 SMPS
Input capacitor C_I(VCC1)	X5R or X7R dielectric		10		µF
Filter capacitor C_O(VDD1)	X5R or X7R dielectric	4	10	12	µF
C_O filter capacitor ESR	f = 3 MHz		10	300	mΩ
Inductor L_O(VDD1)			2.2		µH
L_O inductor dc resistor DCR_L				125	mΩ
VDD2 SMPS
Input capacitor C_I(VCC2)	X5R or X7R dielectric		10		µF
Filter capacitor C_O(VDD2)	X5R or X7R dielectric	4	10	12	µF
C_O filter capacitor ESR	f = 3 MHz		10	300	mΩ
Inductor L_O(VDD2)			2.2		µH
L_O inductor dc resistor DCR_L				125	mΩ
VIO SMPS
Input capacitor C_I(VIO)	X5R or X7R dielectric		10		µF
Filter capacitor C_O(VIO)	X5R or X7R dielectric	4	10	12	µF
C_O filter capacitor ESR	f = 3 MHz		10	300	mΩ
Inductor L_O(VIO)			2.2		µH
L_O inductor dc resistor DCR_L				125	mΩ
VDIG1 LDO
Input capacitor C_I(VCC6)	X5R or X7R dielectric		4.7		µF
Filtering capacitor C_O(VDIG1)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VDIG2 LDO
Filtering capacitor C_O(VDIG2)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VPLL LDO
Input capacitor C_I(VCC5)	X5R or X7R dielectric		4.7		µF
Filtering capacitor C_O(VPLL)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VDAC LDO
Filtering capacitor C_O(VDAC)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VMMC LDO
Input capacitor C_I(VCC4)	X5R or X7R dielectric		4.7		µF
Filtering capacitor C_O(VMMC)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VAUX33 LDO
Filtering capacitor C_O(VAUX33)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VAUX1 LDO
Input capacitor C_I(VCC3)	X5R or X7R dielectric		4.7		µF
Filtering capacitor C_O(VAUX1)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VAUX2 LDO
Filtering capacitor C_O(VAUX2)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VRTC LDO
Input capacitor C_I(VCC7)	X5R or X7R dielectric		4.7		µF
Filtering capacitor C_O(VRTC)		0.8	2.2	2.64	µF
C_O filtering capacitor ESR		0		500	mΩ
VDD3 SMPS
Input capacitor C_I(VDD3)	X5R or X7R dielectric		4.7		µF
Filter capacitor C_O(VDD3)	X5R or X7R dielectric	4	10	12	µF
C_O filter capacitor ESR	f = 1 MHz		10	300	mΩ
Inductor L_O(VDD3)		2.8	4.7	6.6	µH
L_O inductor DC resistor DCR_L			50	500	mΩ
Backup Battery
Backup battery capacitor C_BB	Battery or superCap supplying VBACKUP	5	10	2000	mF
Backup battery capacitor C_BB	Capacitor supplying VBACKUP	1		40	µF
Series resistors	5 to 15 mF	10		1500	Ω
Series resistors	100 to 2000 mF	5		15	Ω
I²C Interfaces
SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1 external pull-up resistor	Connected to VDDIO		1.2		kΩ
Crystal Oscillator (connected from OSC32KIN to OSC32KOUT)
Crystal frequency	at specified load cap value		32.768		kHz
Crystal tolerance	at 27°C	–20	0	20	ppm
Frequency Temperature coefficient.	Oscillator contribution (not including crystal variation)	–0.5		0.5	ppm/°C
Secondary temperature coefficient		–0.04	–0.035	–0.03	ppm/°C²
Voltage coefficient		–2		2	ppm/V
Max crystal series resistor	at fundamental frequency			90	kΩ
Crystal load capacitor	According to crystal data sheet	6		12.5	pF
Load crystal oscillator Coscin, Coscout	parallel mode including parasitic PCB capacitor	12		25	pF
Quality factor		8000		80000

5.4 Thermal Resistance Characteristics for RSL Package

NAME	DESCRIPTION	°C/W⁽¹⁾⁽²⁾
RΘ_JC	Junction-to-case (top)	16.4
RΘ_JB	Junction-to-board	5.6
RΘ_JA (High k PCB)	Junction-to-free air	37
Psi_JT	Junction-to-package top	0.2
Psi_JB	Junction-to-board	5.6
RΘ_JC	Junction-to-case (bottom)	1.3

(1) °C/W = degrees Celsius per watt.

(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(3) m/s = meters per second.

5.5 I/O Pullup and Pulldown Characteristics⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1 Programmable pullup (DFT, default inactive)	Grounded, VDDIO = 1.8 V	–45%	8	+45%	kΩ
SLEEP programmable pulldown (default active)	at 1.8 V, VRTC = 1.8 V	2	4.5	10	µA
PWRHOLD programmable pulldown (default active)	at 1.8 V, VRTC = 1.8 V, VCC7 = 2.7 V	2	4.5	10	µA
PWRHOLD programmable pulldown (default active)	at 5.5 V, VRTC = 1.8 V, VCC7 = 5.5 V	7	14	30	µA
BOOT0, BOOT1 programmable pulldown (default active)	at 1.8 V, VRTC = 1.8 V	2	4.5	10	µA
NRESPWRON pulldown	at 1.8 V, VCC7 = 5.5 V, OFF state	2	4.5	10	µA
32KCLKOUT pulldown (disabled in active-sleep state)	at 1.8 V, VRTC = 1.8 V, OFF state	2	4.5	10	µA
PWRON programmable pullup (default active)	Grounded, VCC7 = 5.5 V	–40	–31	–15	µA
GPIO_CKSYNC programmable pullup (default active)	Grounded, VRTC = 1.8 V	–27	–18	–9	µA

(1) The internal pullups on the CTL-I²C and SR-I²C balls are used for test purposes or when the SR-I²C interface is not used. Discrete pullups to the VIO supply must be mounted on the board in order to use the I²C interfaces. The internal I²C pullups must not be used for functional applications

5.6 Digital I/O Voltage Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
Related I/O: PWRON
Low-level input voltage, V_IL				0.3 x VCC7	V
High-level input voltage, V_IH		0.7 x VCC7			V
Related I/Os: PWRHOLD, GPIO_CKSYNC
Low-level input voltage, V_IL				0.45	V
High-level input voltage, V_IH		1.3	VDDIO/VCC7	VCC7	V
Related I/Os: BOOT0, BOOT1, OSC32KIN
Low-level input voltage, V_IL				0.35 x VRTC	V
High-level input voltage, V_IH		0.65 x VRTC			V
Related I/Os: SLEEP
Low-level input voltage, V_IL				0.35 x VDDIO	V
High-level input voltage, V_IH		0.65 x VDDIO			V
Related I/Os: NRESPWRON, INT1, 32KCLKOUT
Low-level output voltage, V_OL	I_OL = 100 µA			0.2	V
	I_OL = 2 mA			0.45	V
High-level output voltage, V_OH	I_OH = 100 µA	VDDIO – 0.2			V
	I_OH = 2 mA	VDDIO – 0.45			V
Related Open-Drain I/Os: GPIO0
Low-level output voltage, V_OL	I_OL = 100 µA			0.2	V
	I_OL = 2 mA			0.45	V
I²C-Specific Related I/Os: SCL, SDA, SCLSR_EN1, SDASR_EN2
Low-level input voltage, V_IL		–0.5		0.3 x VDDIO	V
High-level input voltage, V_IH		0.7 x VDDIO			V
Hysteresis		0.1 x VDDIO			V
Low-level output voltage, V_OL at 3 mA (sink current), VDDIO = 1.8 V				0.2 × VDDIO	V
Low-level output voltage, V_OL at 3 mA (sink current), VDDIO = 3.3 V				0.4 x VDDIO	V

5.7 I²C Interface and Control Signals

over operating free-air temperature range (unless otherwise noted)

NO.	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX
		INT1 rise and fall times, C_L = 5 to 35 pF	5	10	ns
		NRESPWRON rise and fall times, C_L = 5 to 35 pF	5	10	ns
SLAVE HIGH–SPEED MODE
		SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall time, C_L = 10 to 100 pF	10	80	ns
		Data rate		3.4	Mbps
I3	t_su(SDA-SCLH)	Setup time, SDA valid to SCL high	10		ns
I4	t_h(SCLL-SDA)	Hold time, SDA valid from SCL low	0	70	ns
I7	t_{su(SCLH-SDAL)}	Setup time, SCL high to SDA low	160		ns
I8	t_h(SDAL-SCLL)	Hold time, SCL low from SDA low	160		ns
I9	t_{su(SDAH-SCLH)}	Setup time, SDA high to SCL high	160		ns
SLAVE FAST MODE
		SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall time, C_L = 10 to 400 pF	20 + 0.1 × C_L	250	ns
		Data rate		400	Kbps
I3	t_su(SDA-SCLH)	Setup time, SDA valid to SCL high	100		ns
I4	t_h(SCLL-SDA)	Hold time, SDA valid from SCL low	0	0.9	µs
I7	t_{su(SCLH-SDAL)}	Setup time, SCL high to SDA low	0.6		µs
I8	t_h(SDAL-SCLL)	Hold time, SCL low from SDA low	0.6		µs
I9	t_{su(SDAH-SCLH)}	Setup time, SDA high to SCL high	0.6		µs
SLAVE STANDARD MODE
		SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall time, C_L = 10 to 400 pF		250	ns
		Data rate		100	Kbps
I3	t_su(SDA-SCLH)	Setup time, SDA valid to SCL high			ns
I4	t_h(SCLL-SDA)	Hold time, SDA valid from SCL low	0		µs
I7	t_{su(SCLH-SDAL)}	Setup time, SCL high to SDA low	4.7		µs
I8	t_h(SDAL-SCLL)	Hold time, SCL low from SDA low	4		µs
I9	t_{su(SDAH-SCLH)}	Setup time, SDA high to SCL high	4		µs
SWITCHING CHARACTERISTICS
SLAVE HIGH–SPEED MODE
I1	t_w(SCLL)	Pulse duration, SCL low	160		ns
I2	t_w(SCLH)	Pulse duration, SCL high	60		ns
SLAVE FAST MODE
I1	t_w(SCLL)	Pulse duration, SCL low	1.3		µs
I2	t_w(SCLH)	Pulse duration, SCL high	0.6		µs
SLAVE STANDARD MODE
I1	t_w(SCLL)	Pulse duration, SCL low	4.7		µs
I2	t_w(SCLH)	Pulse duration, SCL high	4		µs

5.8 Power Consumption

over operating free-air temperature range (unless otherwise noted)
All current consumption measurements are relative to the FULL chip, all VCC inputs set to VBAT voltage.

PARAMETER	TEST CONDITIONS	TYP	MAX	UNIT
Device BACKUP state	VBAT = 2.4 V, VBACKUP = 0 V,	11	16	µA
	VBAT = 0 V, VBACKUP = 3.2 V	6	9	µA
Device OFF state	VBAT = 3.6 V, CK32K clock running			µA
	BOOT[1:0] = 00: 32-kHz RC oscillator	16.5	23
	BOOT[1:0] = 01: 32-kHz quartz or bypass oscillator, BOOT0P = 0	15	20
	BOOT[1:0] = 01, Backup Battery Charger on, VBACKUP = 3.2 V	32	42
	VBAT = 5 V, CK32K clock running:	20	28
	BOOT[1:0] = 00: RC oscillator
Device SLEEP state	VBAT = 3.6 V, CK32K clock running, PWRHOLDP = 0			µA
	BOOT[1:0] = 00, 3 DC-DCs on, 5 LDOs and VRTC on, no load	295
	BOOT[1:0] = 01, 3 DC-DCs on, 3 LDOs and VRTC on, no load, BOOT0P = 0	279
Device ACTIVE state	VBAT = 3.6 V, CK32K clock running, PWRHOLDP = 0			mA
	BOOT[1:0] = 00, 3 DC-DCs on, 5 LDOs and VRTC on, no load	1
	BOOT[1:0] = 01, 3 DC-DCs on, 3 LDOs and VRTC on, no load, BOOT0P = 0	0.9
	BOOT[1:0] = 00, 3 DC-DCs on PWM mode (VDD1_PSKIP = VDD2_PSKIP = VIO_PSKIP = 0), 5 LDOs and VRTC on, no load	21

5.9 Power References and Thresholds

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Output reference voltage (VREF terminal)	Device in active or low-power mode	–1%	0.85	+1%	V
Main battery charged threshold VMBCH (programmable)	Measured on VCC7 terminal Triggering monitored through NRESPRWON
	VMBCH_VSEL = 11, BOOT[1:0] = 11 or 00		3		V
	VMBCH_VSEL = 10		2.9
	VMBCH_VSEL = 01		2.8
	VMBCH_VSEL = 00		bypassed
Main battery discharged threshold VMBDCH (programmable)	Measured on VCC7 terminal (MTL prg) Triggering monitored through INT1		VMBCH – 100 mV		V
Main battery low threshold VMBLO (MB comparator)	Measured on VCC7 terminal (Triggering monitored on terminal NRESPWRON)	2.5	2.6	2.7	V
Main battery high threshold VMBHI	VBACKUP = 0 V, measured on terminal VCC7 (MB comparator)	2.6	2.75	3	V
	VBACKUP = 3.2 V, measured on terminal VCC7	2.5	2.55	3	V
Main battery not present threshold VBNPR	Measured on terminal VCC7 (Triggering monitored on terminal VRTC)	1.9	2.1	2.2	V
Ground current (analog references + comparators + backup battery switch)	V_CC = 3.6 V
	Device in OFF state		8		µA
	Device in ACTIVE or SLEEP state		20		µA

5.10 Thermal Monitoring and Shutdown

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Hot-die temperature rising threshold	THERM_HDSEL[1:0] = 00		117		°C
	THERM_HDSEL[1:0] = 01		121
	THERM_HDSEL[1:0] = 10	113	125	136
	THERM_HDSEL[1:0] = 11		130
Hot-die temperature hysteresis			10		°C
Thermal shutdown temperature rising threshold		136	148	160	°C
Thermal shutdown temperature hysteresis			10		°C
Ground current	Device in ACTIVE state, Temp = 27°C, VCC7 = 3.6 V		6		µA

5.11 32-kHz RTC Clock

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
CLK32KOUT rise and fall time	C_L = 35 pF			10	ns
Bypass Clock (OSC32KIN: input, OSC32KOUT floating)
Input bypass clock frequency	OSCKIN input		32		kHz
Input bypass clock duty cycle	OSCKIN input	40%		60%
Input bypass clock rise and fall time	10% – 90%, OSC32KIN input		10	20	ns
CLK32KOUT duty cycle	Logic output signal	40%		60%
Bypass clock setup time	32KCLKOUT output			1	ms
Ground current	Bypass mode			1.5	µA
Crystal oscillator (connected from OSC32KIN to OSC32KOUT)
Output frequency	CK32KOUT output		32.768		kHz
Oscillator startup time	On power on			2	s
Ground current			1.5		µA
RC oscillator (OSC32KIN: grounded, OSC32KOUT floating)
Output frequency	CK32KOUT output		32		kHz
Output frequency accuracy	at 25°C	–15%	0%	+15%
Cycle jitter (RMS)	Oscillator contribution			+10%
Output duty cycle		+40%	+50%	+60%
Settling time				150	µs
Ground current	Active at fundamental frequency		4		µA

5.12 Backup Battery Charger

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Backup battery charging current	VBACKUP = 0 to 2.4 V, BBCHEN = 1	350	500	700	µA
End-of-charge backup battery voltage⁽¹⁾	VCC7 = 3.6 V, BBSEL = 10	–3%	3.15	+3%	V
	VCC7 = 3.6 V, BBSEL = 00	–3%	3	+3%
	VCC7 = 3.6 V, BBSEL = 01	–3%	2.52	+3%
	VCC7 = 3.6 V, BBSEL = 11	VBAT – 0.3 V		VBAT
Ground current	On mode		10		µA

(1) Note:

BBSEL = 10, 00, or 01 intended to charge battery or superCap
BBSEL = 11 intended to charge capacitor

5.13 VRTC LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage V_IN	On mode	2.5		5.5	V
	Back-up mode	1.9		5.5	V
DC output voltage V_OUT	On mode, 3.0 V < V_IN < 5.5 V	1.78	1.83	1.88	V
	Back-up mode, 2.3 V ≤ V_IN ≤ 2.6 V	1.72	1.78	1.84	V
Rated output current I_OUTmax	On mode	20			mA
	Back-up mode	0.1			mA
DC load regulation	On mode, I_OUT = I_OUTmax to 0			50	mV
	Back-up mode, I_OUT = I_OUTmax to 0			50	mV
DC line regulation	On mode, V_IN = 3.0 V to V_INmax at I_OUT = I_OUTmax			2.5	mV
	Back-up mode, V_IN = 2.3 V to 5.5 V at I_OUT = I_OUTmax			25	mV
Transient load regulation	On mode, V_IN = V_INmin + 0.2 V to V_INmax			50⁽¹⁾	mV
	I_OUT = I_OUTmax/2 to I_OUTmax in 5 µs and I_OUT = I_OUTmax to I_OUTmax/2 in 5 µs
Transient line regulation	On mode, V_IN = V_INmin + 0.5 V to V_INmin in 30 µs			25⁽¹⁾	mV
	And V_IN = V_INmin to V_INmin + 0.5 V in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, V_IN rising from 0 up to 3.6 V, at V_OUT = 0.1 V up to V_OUTmin		2.2		ms
Ripple rejection	V_IN = V_INDC + 100 mV_pp tone, V_INDC+ = V_INmin + 0.1 V to V_INmax at I_OUT = I_OUTmax/2
	f = 217 Hz		55		dB
	f = 50 kHz		35		dB
Ground current	Device in ACTIVE state		23		µA
	Device in BACKUP or OFF state		3		µA

(1) These parameters are not tested. They are used for design specification only.

5.14 VIO SMPS

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage (VCCIO and VCC7) V_IN	I_OUT ≤ 800 mA	2.7		5.5	V
	V_OUT = 1.5 V or 1.8 V, I_OUT > 800 mA	3.2		5.5
	V_OUT = 2.5 V, I_OUT > 800 mA	4.0		5.5
	V_OUT = 3.3 V, I_OUT > 800 mA	4.4		5.5
DC output voltage (V_OUT)	PWM mode (VIO_PSKIP = 0) or pulse skip mode I_OUT to I_MAX
	VSEL=00	–3%	1.5	+3%	V
	VSEL = 01, default BOOT[1:0] = 00 and 01	–3%	1.8	+3%
	VSEL = 10	–3%	2.5	+3%
	VSEL = 11	–3%	3.3	+3%
	Power down		0
Rated output current I_OUTmax	ILMAX[1:0] = 00, default	500			mA
	ILMAX[1:0] = 01	1000			mA
P-channel MOSFET	V_IN = V_INmin		300		mΩ
On-resistance R_{DS(ON)_PMOS}	V_IN = 3.8 V		250	400	mΩ
P-channel leakage current I_{LK_PMOS}	V_IN = V_INMAX, SWIO = 0 V			2	µA
N-channel MOSFET	V_IN = V_MIN		300		mΩ
On-resistance R_{DS(ON)_NMOS}	V_IN = 3.8 V		250	400	mΩ
N-channel leakage current I_{LK_NMOS}	V_IN = V_INmax, SWIO = V_INmax			2	µA
PMOS current limit (high-side)	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 00	650			mA
	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 01	1200
	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 10	1700
NMOS current limit (low-side)	Source current load:				mA
	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 00	650
	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 01	1200
	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 10	1700
	Sink current load:
	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 00	800
	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 01	1200
	V_IN = V_INmin to V_INmax, ILMAX[1:0] = 10	1700
DC load regulation	On mode, I_OUT = 0 to I_OUTmax			20	mV
DC line regulation	On mode, V_IN = V_INmin to V_INmax			20	mV
Transient load regulation	V_IN = 3.8 V, V_OUT = 1.8 V			50	mV
	I_OUT = 0 to 500 mA , Max slew = 100 mA/µs			50	mV
	I_OUT = 700 to 1200 mA , Max slew = 100 mA/µs
t on, off to on	I_OUT = 200 mA		350		µs
Overshoot	SMPS turned on		3%
Power-save mode Ripple voltage	Pulse skipping mode, I_OUT = 1 mA		0.025 × V_OUT		V_PP
Switching frequency			3		MHz
Duty cycle				100	%
Minimum On Time T_ON(MIN)			35		ns
P-channel MOSFET
VFBIO internal resistance		0.5	1		MΩ
Discharge resistor for power-down sequence R_DIS	During device switch-off sequence		30	50	Ω
	Note: No discharge resistor is applied if VIO is turned off while the device is on.
Ground current (I_Q)	Off			1	µA
	PWM mode, I_OUT = 0 mA, V_IN = 3.8 V, VIO_PSKIP = 0		7500
	Pulse skipping mode, no switching, 3-MHz clock on		250
	Low-power (pulse skipping) mode, no switching
	ST[1:0]=11		63
Conversion efficiency	PWM mode, DCR_L < 50 mΩ, V_OUT = 1.8 V, V_IN = 3.6 V:
	I_OUT = 10 mA		44%
	I_OUT = 100 mA		87%
	I_OUT = 400 mA		86%
	I_OUT = 800 mA		76%
	I_OUT = 1000 mA		72%
	Pulse Skipping mode, DCR_L < 50 mΩ, V_OUT = 1.8 V, V_IN = 3.6 V:
	I_OUT = 1 mA		71%
	I_OUT = 10 mA		80%
	I_OUT = 200 mA		87%

5.15 VDD1 SMPS

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage (VCC1 and VCC7) V_IN	I_OUT ≤ 1200 mA	2.7		5.5	V
	V_OUT = 0.6 V to 1.5 V, VGAIN_SEL = 00, I_OUT > 1200 mA	V_OUT + 2 V		5.5
	2.5 V ≤ V_OUT ≤ 3.3 V, VGAIN_SEL = 10 or 11, I_OUT > 1200 mA	4.5		5.5
DC output voltage (V_OUT)	VGAIN_SEL = 00, I_OUT = 0 to I_OUTmax:
	max programmable voltage, SEL[6:0] = 1001011		1.5		V
	default voltage, BOOT[1:0] = 00	–3%	1.2	+3%
	default voltage, BOOT[1:0] = 01	–3%	1.2	+3%
	min programmable voltage, SEL[6:0] = 0000011		0.6
	SEL[6:0] = 000000: power down		0
	VGAIN_SEL = 10, SEL = 0101011 = 43, I_OUT = 0 to I_OUTmax	–3%	2.2	+3%	V
	VGAIN_SEL = 11, SEL = 0101000 = 40, I_OUT = 0 to I_OUTmax	–3%	3.2	+3%	V
DC output voltage programmable step (V_OUTSTEP)	VGAIN_SEL = 00, 72 steps		12.5		mV
Rated output current I_OUTmax	ILMAX = 0, default	1000			mA
	ILMAX = 1	1500
P-channel MOSFET	V_IN = V_INmin		300		mΩ
On-resistance R_{DS(ON)_PMOS}	V_IN = 3.8 V		250	400	mΩ
P-channel leakage current	V_IN = V_INmax, SW1 = 0 V			2	µA
I_{LK_PMOS}
N-channel MOSFET	V_IN = V_MIN		300		mΩ
On-resistance R_{DS(ON)_NMOS}	V_IN = 3.8 V		250	400	mΩ
N-channel leakage current I_{LK_NMOS}	V_IN = V_INmax, SW1 = V_INmax			2	µA
PMOS current limit (high-side)	V_IN = V_INmin to V_INmax, ILMAX = 0	1150			mA
	V_IN = V_INmin to V_INmax, ILMAX = 1	2000			mA
NMOS current limit (low-side)	Source current load:				mA
	V_IN = V_INmin to V_INmax, ILMAX = 0	1150
	V_IN = V_INmin to V_INmax, ILMAX = 1	2000
	Sink current load:
	V_IN = V_INmin to V_INmax, ILMAX = 0	1200
	V_IN = V_INmin to V_INmax, ILMAX = 1	2000
DC load regulation	On mode, I_OUT = 0 to I_OUTmax			20	mV
DC line regulation	On mode, V_IN = V_INmin to V_INmax			20	mV
Transient load regulation	V_IN = 3.8 V, V_OUT = 1.2 V
	I_OUT = 0 to 500 mA , Max slew = 100 mA/µs			50	mV
	I_OUT = 700 mA to 1.2A , Max slew = 100 mA/µs
t on, off to on	I_OUT = 200 mA		350		µs
Output voltage transition rate	From V_OUT = 0.6 V to 1.5 V and V_OUT = 1.5 V to 0.6 V I_OUT = 500 mA
	TSTEP[2:0] = 001		12.5		mV/µs
	TSTEP[2:0] = 011 (default)		7.5
	TSTEP[2:0] = 111		2.5
Overshoot	SMPS turned on		3%
Power-save mode ripple voltage	Pulse skipping mode, I_OUT = 1 mA		0.025 × V_OUT		V_PP
Switching frequency			3		MHz
Duty cycle				100	%
Minimum on time t_ON(MIN)			35		ns
P-channel MOSFET
VFB1 internal resistance		0.5	1		MΩ
Discharge resistor for power-down sequence R_DIS			30	50	Ω
Ground current (I_Q)	Off			1	µA
	PWM mode, I_OUT = 0 mA, V_IN = 3.8 V, VDD1_PSKIP = 0		7500
	Pulse skipping mode, no switching		78
	Low-power (pulse skipping) mode, no switching
	ST[1:0] = 11		63
Conversion efficiency	PWM mode, DCR_L < 0.1 Ω, V_OUT = 1.2 V, V_IN = 3.6 V:
	I_OUT = 10 mA		35%
	I_OUT = 200 mA		82%
	I_OUT = 400 mA		81%
	I_OUT = 800 mA		74%
	I_OUT = 1500 mA		62%
	Pulse skipping mode, DCR_L < 0.1Ω, V_OUT = 1.2 V, V_IN = 3.6 V:
	I_OUT = 1 mA		59%
	I_OUT = 10 mA		70%
	I_OUT = 200 mA		82%

5.16 VDD2 SMPS

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage (VCC2 and VCC4) V_IN	I_OUT ≤ 1200 mA	2.7		5.5	V
	V_OUT = 0.6 V to 1.5 V, VGAIN_SEL = 00, I_OUT > 1200 mA	V_OUT + 2 V		5.5
	2.5 V ≤ V_OUT ≤ 3.3 V, VGAIN_SEL = 10 or 11, I_OUT > 1200 mA	4.5		5.5
DC output voltage (V_OUT)	VGAIN_SEL = 00, I_OUT = 0 to I_OUTmax:
	max programmable voltage, SEL[6:0] = 1001011		1.5		V
	default, BOOT[1:0] = 01	–3%	1.2	+3%
	min programmable voltage, SEL[6:0] = 0000011		0.6
	SEL[6:0] = 000000: power down		0
	VGAIN_SEL = 10, SEL = 0101011 = 43	–3%	2.2	+3%
	VGAIN_SEL = 11, default, BOOT[1:0] = 00	–3%	3.3	+3%
DC output voltage programmable step (V_OUTSTEP)	VGAIN_SEL = 00, 72 steps		12.5		mV
Rated output current I_OUTmax	ILMAX = 0, default	1000			mA
	ILMAX = 1	1500
P-channel MOSFET	V_IN = V_INmin		300		mΩ
On-resistance R_{DS(ON)_PMOS}	V_IN = 3.8 V		250	400	mΩ
P-channel leakage current I_{LK_PMOS}	V_IN = V_INmax, SW2 = 0 V			2	µA
N-channel MOSFET	V_IN = V_MIN		300		mΩ
On-resistance R_{DS(ON)_NMOS}	V_IN = 3.8 V		250	400	mΩ
N-channel leakage current I_{LK_NMOS}	V_IN = V_INmax, SW2 = V_INmax			2	µA
PMOS current limit (high-side)	V_IN = V_INmin to V_INmax, ILMAX = 0	1150			mA
	V_IN = V_INmin to V_INmax, ILMAX = 1	2200			mA
NMOS current limit (low-side)	Source current load:	1150			mA
	V_IN = V_INmin to V_INmax, ILMAX = 0	2000
	V_IN = V_INmin to V_INmax, ILMAX = 1
	Sink current load:
	V_IN = V_INmin to V_INmax, ILMAX = 0	1200
	V_IN = V_INmin to V_INmax, ILMAX = 1	2000
DC load regulation	On mode, I_OUT = 0 to I_OUTmax			20	mV
DC line regulation	On mode, V_IN = V_INmin to V_INmax at I_OUT = I_OUTmax			20	mV
Transient load regulation	V_IN = 3.8 V, V_OUT = 1.2 V			50	mV
	I_OUT = 0 to 500 mA , Max slew = 100 mA/µs
	I_OUT = 700 mA to 1.2 A , Max slew = 100 mA/µs
t on, off to on	I_OUT = 200 mA		350		µs
Output voltage transition rate	From V_OUT = 0.6 V to 1.5 V and V_OUT = 1.5 V to 0.6 V I_OUT = 500 mA
	TSTEP[2:0] = 001		12.5		µs
	TSTEP[2:0] = 011 (default)		7.5
	TSTEP[2:0] = 111		2.5
Power-save mode ripple voltage	Pulse skipping mode, I_OUT = 1 mA		0.025 V_OUT		V_PP
Overshoot			3%
Switching frequency			3		MHz
Duty cycle				100	%
Minimum On time			35		ns
P-Channel MOSFET			35		ns
VFB2 internal resistance		0.5	1		MΩ
Discharge resistor for power-down sequence R_DIS			30	50	Ω
Ground current (I_Q)	Off			1	µA
	PWM mode, I_OUT = 0 mA, V_IN = 3.8 V, VDD2_PSKIP = 0		7500
	Pulse skipping mode, no switching		78
	Low-power (pulse skipping) mode, no switching
	ST[1:0] = 11		63
Conversion efficiency	PWM mode, DCR_L < 50 mΩ, V_OUT = 1.2 V, V_IN = 3.6 V:
	I_OUT = 10 mA		35%
	I_OUT = 200 mA		82%
	I_OUT = 400 mA		81%
	I_OUT = 800 mA		74%
	I_OUT = 1200 mA		66%
	I_OUT = 1500 mA		62%
	Pulse skipping mode mode, DCR_L < 50 mΩ, V_OUT = 1.2 V, V_IN = 3.6 V:
	I_OUT = 1 mA		59%
	I_OUT = 10 mA		70%
	I_OUT = 200 mA		82%
	PWM mode, DCR_L < 50 mΩ, V_OUT = 3.3 V, V_IN = 5 V:
	I_OUT = 10 mA		44%
	I_OUT = 200 mA		90%
	I_OUT = 400 mA		91%
	I_OUT = 800 mA		88%
	I_OUT = 1200 mA		84%
	I_OUT = 1500 mA		81%
	Pulse skipping mode mode, DCR_L < 50 mΩ, V_OUT = 3.3 V, V_IN = 5 V:
	I_OUT = 1 mA		75%
	I_OUT = 10 mA		83%
	I_OUT = 200 mA		90%

5.17 VDD3 SMPS

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage V_IN		3		5.5	V
DC output voltage (V_OUT)		4.65	5	5.25	V
Rated output current I_OUTmax		100			mA
N-channel MOSFET	V_IN = 3.6 V		500		mΩ
On-resistance R_{DS(ON)_NMOS}
N-channel MOSFET leakage current I_{LK_NMOS}	V_IN = V_INmax, SW3 = V_INmax			2	µA
N-channel MOSFET DC current limit	V_IN = V_INmin to V_INmax, sink current load	430	550		mA
Turn-on inrush current	V_IN = V_INmin to V_INmax			850	mA
Ripple voltage			20		mV
DC load regulation	On mode, I_OUT = 0 to I_OUTmax			100	mV
DC line regulation	On mode, V_IN = V_INmin to 5 V at I_OUT = I_OUTmax			100	mV
Turn-on time	I_OUT = 8 mA, V_OUT = 0 to 4.4 V		200		µs
Overshoot			3%
Switching frequency			1		MHz
VFB3 internal resistance			088		MΩ
Ground current (I_Q)	Off			1	µA
	I_OUT = 0 mA to I_OUTmax, V_IN = 3.6 V		360		µA
Conversion efficiency	V_IN = 3.6 V:
	I_OUT = 10 mA		81%
	I_OUT = 50 mA		85%
	I_OUT = 100 mA		85%

5.18 VDIG1 and VDIG2 LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage (VCC6) V_IN	V_OUT (VDIG1) = 1.2 V at 300 mA / 1.5 V at 100 mA and				V
	V_OUT (VDIG2) = 1.2 V / 1.1 V / 1.0 V at 300 mA	1.7		5.5
	V_OUT (VDIG1) = 1.5 V and V_OUT (VDIG2) = 1.8 V at 200mA	2.1		5.5
	V_OUT (VDIG1) = 1.8 V and V_OUT (VDIG2) = 1.8 V	2.7		5.5
	V_OUT (VDIG1) = 2.7 V	3.2		5
VDIG1
DC output voltage V_OUT	On and Low-power mode, V_IN = V_INmin to V_INmax
	SEL = 11, I_OUT = 0 to I_OUTmax	–3%	2.7	+3%	V
	SEL = 10 I_OUT = 0 to I_OUTmax	–3%	1.8	+3%
	SEL = 01 I_OUT = 0 to 100 mA/I_OUTmax	–3%	1.5	+3%
	SEL = 00, I_OUT = 0 to I_OUTmax, V_IN = V_INmin to 4 V, default BOOT[1:0] = 00 or 01	–3%	1.2	+3%
Rated output current I_OUTmax	On mode	300			mA
	Low-power mode	1			mA
Load current limitation (short-circuit protection)	On mode, V_OUT = V_OUTmin – 100 mV	350	600		mA
Dropout voltage V_DO	On mode, VDO = V_IN – V_OUT
	V_OUTtyp = 2.7 V, V_IN = 2.8 V, I_OUT = I_OUTmax, T = 25°C		150		mV
	V_OUTtyp = 1.5 V, V_IN = 1.7 V, I_OUT = I_OUTmax, T = 25°C		300		mV
DC load regulation	On mode, I_OUT = I_OUTmax to 0			25	mV
DC line regulation	On mode, V_IN = V_INmin to V_INmax at I_OUT = I_OUTmax			3	mV
Transient load regulation	On mode, V_IN = 3.8 V		10		mV
	I_OUT = 20 mA to 180 mA in 5µs and I_OUT = 180 mA to 20 mA in 5 µs
Transient line regulation	On mode, V_IN = 2.7 + 0.5 V to 2.7 in 30 µs,		2		mV
	And V_IN = 2.7 to 2.7 + 0.5 V in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, at V_OUT = 0.1 V up to V_OUTmin		100		µs
Turn-on inrush current			300		mA
Ripple rejection	V_IN = V_INDC + 100 mV_pp tone, _VINDC+= 3.8 V, I_OUT = I_OUTmax/2
	f = 217 Hz		70		dB
	f = 50 kHz		40		dB
VDIG1 internal resistance	LDO off		400		Ω
Ground current	On mode, I_OUT = 0, VCC6 = VBAT, V_OUT = 2.7 V		54		µA
	On mode, I_OUT = 0, VCC6 = 1.8 V, V_OUT = 1.2 V		67
	On mode, I_OUT = I_OUTmax, VCC6 = VBAT, V_OUT = 2.7 V		1870
	On mode, I_OUT = I_OUTmax, VCC6 = 1.8 V, V_OUT = 1.2 V		1300
	Low-power mode, VCC6 = VBAT, V_OUT = 2.7 V		13
	Low-power mode, VCC6 = 1.8 V, V_OUT = 1.2 V		10
	Off mode			1
VDIG2
DC output voltage V_OUT	On and low-power mode, V_IN = V_INmin to V_INmax
	SEL = 11, I_OUT = 0 to I_OUTmax	–3%	1.8	+3%	V
	SEL = 10 I_OUT = 0 to I_OUTmax, V_IN = V_INmin to 4 V	–3%	1.2	+3%
	SEL = 01 I_OUT = 0 to 100 mA/I_OUTmax, V_IN= V_INmin to 4 V	–3%	1.1	+3%
	SEL = 00, I_OUT = 0 to I_OUTmax, V_IN = V_INmin to 4 V, default BOOT[1:0] = 00 or 01	–3%	1	+3%
Rated output current I_OUTmax	On mode	300			mA
	Low-power mode	1
Load current limitation (short-circuit protection)	On mode, V_OUT = V_OUTmin – 100 mV	350	600		mA
Dropout voltage V_DO	On mode, V_DO = V_IN – V_OUT,
	V_OUTtyp = 1.8 V, V_IN = 2.1 V, IOUT=I_OUTmax, T = 25°C		250		mV
DC load regulation	On mode, I_OUT = I_OUTmax to 0			25	mV
DC line regulation	On mode, V_IN = V_INmin to V_INmax at I_OUT = I_OUTmax			3	mV
Transient load regulation	On mode, V_IN = 3.8 V		10		mV
	I_OUT = 20 mA to 180 mA in 5 µs and I_OUT = 180 mA to 20 mA in 5 µs
Transient line regulation	On mode, V_IN = 2.7 + 0.5 V to 2.7 in 30 µs,		2		mV
	And V_IN = 2.7 to 2.7 + 0.5 V in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, at V_OUT = 0.1 V up to V_OUTmin		100		µs
Turn-on inrush current			300		mA
Ripple rejection	V_IN = V_INDC + 100 mV_pp tone, _VINDC+= 3.8 V, I_OUT = I_OUTmax/2
	f = 217 Hz		70		dB
	f = 50 kHz		40		dB
VDIG2 internal resistance	LDO off		400		Ω
Ground current	On mode, I_OUT = 0, VCC6 = VBAT, V_OUT = 1.8 V		52		µA
	On mode, I_OUT = 0, VCC6 = 1.8 V, V_OUT = 1.0 V		67
	On mode, I_OUT = I_OUTmax, VCC6 = VBAT, V_OUT = 1.8 V		1750
	On mode, I_OUT = I_OUTmax, VCC6 = 1.8 V, V_OUT = 1.0 V		1300
	Low-power mode, VCC6 = VBAT, V_OUT = 1.8 V		11
	Low-power mode, VCC6 = 1.8 V, V_OUT = 1.0 V		10
	Off mode			1

5.19 VAUX33 and VMMC LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage (VCC3) V_IN	V_OUT (VAUX33) = 1.8 V / 2 V and V_OUT (VMMC) = 1.8 V	2.7		5.5	V
	V_OUT (VAUX33) = 2.8 V	3.2		5.5
	V_OUT (VAUX33) = 3.3 V	3.6		5.5
	V_OUT (VMMC) = 2.8 V at 200 mA	3.2		5.5
	V_OUT (VMMC) = 3.0 V	3.6		5.5
	V_OUT (VMMC) = 3.3 V at 200 mA	3.6		5.5
VAUX33
DC output voltage V_OUT	On and low-power mode, V_IN = V_INmin to V_INmax
	SEL = 11, I_OUT = 0 to I_OUTmax, Default BOOT[1:0] = 01	–3%	3.3	+3%	V
	SEL = 10, I_OUT = 0 to I_OUTmax	–3%	2.8	+3%
	SEL = 01, I_OUT = 0 to I_OUTmax	–3%	2.0	+3%
	SEL = 00, I_OUT = 0 to I_OUTmax, default BOOT[1:0] = 00	–3%	1.8	+3%
Rated output current I_OUTmax	On mode	150			mA
	Low-power mode	1			mA
Load current limitation (short-circuit protection)	On mode, V_OUT = V_OUTmin – 100 mV	350	500		mA
Dropout Voltage V_DO	On mode, V_OUTtyp = 2.8 V, V_DO = V_IN – V_OUT,
	V_IN = 2.9 V, I_OUT = I_OUTmax, T = 25°C		150		mV
DC load regulation	On mode, I_OUT = I_OUTmax to 0			20	mV
DC line regulation	On mode, I_OUT = I_OUTmax			3	mV
Transient load regulation	On mode, V_IN = 3.8 V		12		mV
	I_OUT = 0.1 × I_OUTmax to 0.9 × I_OUTmax in 5 µs and I_OUT = 0.9 × I_OUTmax to 0.1 × I_OUTmax in 5 µs
Transient line regulation	On mode, I_OUT = I_OUTmax,V_IN = V_INmin + 0.5 V to V_INmin in 30 µs		2		mV
	and V_IN = V_INmin to V_INmin + 0.5 V in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, at V_OUT = 0.1 V up to V_OUTmin		100		µs
Turn-on inrush current			600		mA
Ripple Rejection	V_IN = V_INDC + 100 mV_pp tone, V_INDC+ = 3.8 V, I_OUT = I_OUTmax/2
	f = 217 Hz		70		dB
	f = 50 kHz		40		dB
VAUX33 internal resistance	LDO off		70		Ω
Ground current	On mode, I_OUT = 0		55		µA
	On mode, I_OUT = I_OUTmax		1600
	Low-power mode		15
	Off mode			1
VMMC
DC output voltage V_OUT	On and low-power mode, V_IN = V_INmin to V_INmax
	SEL = 11, I_OUT = 0 to 200 mA, default BOOT[1:0] = 00	–3%	3.3	+3%	V
	SEL = 10, I_OUT = 0 to I_OUTmax	–3%	3.0	+3%
	SEL = 01, I_OUT = 0 to 200 mA	–3%	2.8	+3%
	SEL = 00, I_OUT = 0 to I_OUTmax, default BOOT[1:0] = 01	–3%	1.8	+3%
Rated output current I_OUTmax	On mode	300			mA
	Low-power mode	1			mA
Load current limitation (short-circuit protection)	On mode, V_OUT = V_OUTmin – 100 mV	350	500		mA
Dropout voltage V_DO	Dropout voltage V_DO
	V_IN = 3.0 V, I_OUT = 200 mA, T = 25°C		200		mV
DC load regulation	On mode, I_OUT = I_OUTmax to 0			25	mV
DC line regulation	On mode, V_IN = V_INmin to V_INmax at I_OUT = I_OUTmax			3	mV
Transient load regulation	On mode, V_IN = 3.8 V		12		mV
	I_OUT = 20 mA to 180 mA in 5 µs and I_OUT = 180 mA to 20 mA in 5 µs
Transient line regulation	On mode, I_OUT = 200 mA, V_IN = V_INmin + 0.5 V to V_INmin in 30 µs		2		mV
	And V_IN = V_INmin to V_INmin + 0.5 V in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, at V_OUT = 0.1 V up to V_OUTmin		100		µs
Ripple rejection	V_IN = V_INDC + 100 mV_pp tone, V_INDC+= 3.8 V, I_OUT = I_OUTmax/2
	f = 217 Hz		70		dB
	f = 50 kHz		40		dB
VMMC internal resistance	LDO Off		70		Ω
Ground current	On mode, I_OUT = 0		55		µA
	On mode, I_OUT = I_OUTmax		2700
	Low-power mode		15
	Off mode			1

5.20 VAUX1 and VAUX2 LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage (VCC4) V_IN	V_OUT (VAUX1) = 1.8 V and V_OUT (AUX2) = 1.8 V	2.7		5.5	V
	V_OUT (VAUX1) = 2.5 V	3.2		5.5
	V_OUT (VAUX1) = 2.8 V at I_load = 200 mA and 2.85 V at I_load = 200mA	3.2		5.5
	V_OUT (VAUX2) = 2.8 V	3.2		5.5
	V_OUT (VAUX2) = 2.9 V at I_load = 100mA	3.2		5.5
	V_OUT (VAUX2) = 3.3 V	3.6		5.5
VAUX1
DC output voltage V_OUT	On and low-power mode, V_IN = V_INmin to V_INmax
	SEL = 11, I_OUT = 0 to 200 mA	–3%	2.85	+3%	V
	SEL = 10, I_OUT = 0 to 200 mA	–3%	2.8	+3%
	SEL = 01, I_OUT = 0 to I_OUTmax	–3%	2.5	+3%
	SEL = 00, I_OUT = 0 to I_OUTmax, default BOOT[1:0] = 00 or 01	–3%	1.8	+3%
Rated output current I_OUTmax	On mode	300			mA
	Low-power mode	1			mA
Load current limitation (short-circuit protection)	On mode, V_OUT = V_OUTmin – 100 mV	350	500		mA
Dropout voltage V_DO	On mode, V_OUTtyp = 2.8 V, V_DO = V_IN – V_OUT,
	V_IN = 3.0 V, I_OUT = 200 mA, T = 25°C		200		mV
DC load regulation	On mode, I_OUT = 200 mA to 0			15	mA
DC line regulation	On mode, I_OUT = 200 mA			5	V
Transient load regulation	On mode, V_IN = 3.8 V, I_OUT = 20 mA to 180 mA in 5 µs		15		mV
	and I_OUT = 180 mA to 20 mA in 5µs
Transient line regulation	On mode, I_OUT = 200 mA, V_IN= V_INmin + 0.5 V to V_INmin in 30 µs		2		mV
	and V_IN= V_INmin to V_INmin + 0.5v in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, at V_OUT = 0.1 V up to V_OUTmin, no load		100		µs
Turn-on inrush current			600		mA
Ripple Rejection	V_IN = V_INDC + 100 mV_pp tone, V_INDC+ = 3.8 V, I_OUT = I_OUTmax/2
	f = 217 Hz		70		dB
	f = 50 kHz		40		dB
VAUX1 internal resistance	LDO Off		80		Ω
Ground current	On mode, I_OUT = 0		60		µA
	On mode, I_OUT = I_OUTmax		2700
	Low-power mode		12
	Off mode			1
VAUX2
	On and low-power mode, V_IN = V_INmin to V_INmax
	SEL = 11, I_OUT = 0 to I_OUTmax	–3%	3.3	+3%	V
	SEL = 10, I_OUT = 0 to 100 mA	–3%	2.9	+3%
	SEL = 01, I_OUT = 0 to I_OUTmax	–3%	2.8	+3%
	SEL = 00, I_OUT = 0 to I_OUTmax, default BOOT[1:0] = 00 or 01	–3%	1.8	+3%
Rated output current I_OUTmax	On mode	300			mA
	Low-power mode	1			mA
Load current limitation (short-circuit protection)	On mode, V_OUT = V_OUTmin – 100 mV	350	500		mA
Dropout voltage V_DO	On mode, V_OUTtyp = 2.8 V, V_DO = V_IN – V_OUT		150		mV
	V_IN = 2.9 V, I_OUT = I_OUTmax, T = 25°C
DC load regulation	On mode, I_OUT = I_OUTmax to 0			15	mV
DC line regulation	On mode, V_IN = V_INmin to V_INmax at I_OUT = I_OUTmax			2	mV
Transient load regulation	On mode, V_IN = 3.8 V, I_OUT = 0.1 × I_OUTmax to 0.9 × I_OUTmax in 5µs		12		mV
	And I_OUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5us
Transient line regulation	On mode, I_OUT = I_OUTmax, V_IN = V_INmin + 0.5 V to V_INmin in 30 µs		2		mV
	And V_IN= V_INmin to V_INmin + 0.5 V in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, at V_OUT = 0.1 V up to V_OUTmin		100		µs
Turn-on Inrush current			600		mA
Ripple rejection	V_IN = V_INDC + 100 mV_pp tone, V_INDC+ = 3.8 V, I_OUT = I_OUTmax/2
	f = 217 Hz		70		dB
	f = 50 kHz		40		dB
VAUX2 internal resistance	LDO off		80		Ω
Ground current	On mode, I_OUT = 0		60		µA
	On mode, I_OUT = I_OUTmax		1600
	Low-power mode		12
	Off mode			1

5.21 VDAC and VPLL LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input voltage (VCC5) V_IN	V_OUT(VDAC) = 1.8 V and V_OUT(VPLL) = 1.8 V / 1.1 V / 1.0 V	2.7		5.5	V
	V_OUT(VDAC) = 2.6 V and V_OUT(VPLL) = 2.5 V	3.0		5.5
	V_OUT(VDAC) = 2.8 V / 2.85 V	3.2		5.5
VDAC
DC Output voltage V_OUT	On and low-power mode, V_IN = V_INmin to V_INmax
	SEL = 11, I_OUT = 0 to I_OUTmax	–3%	2.85	+3%	V
	SEL = 10, I_OUT = 0 to I_OUTmax	–3%	2.8	+3%
	SEL = 01, I_OUT = 0 to I_OUTmax	–3%	2.6	+3%
	SEL = 00, I_OUT = 0 to I_OUTmax, default BOOT[1:0] = 00 or 01	–3%	1.8	+3%
Rated output current I_OUTmax	On mode	150			mA
	Low-power mode	1			mA
Load current limitation (short-circuit protection)	On mode, V_OUT = V_OUTmin – 100 mV	350	500		mA
Dropout Voltage V_DO	On mode, V_OUTtyp = 2.8 V, V_DO = V_IN – V_OUT,		150		mV
	V_IN = 2.9 V, I_OUT = I_OUTmax, T = 25°C
DC load regulation	On mode, V_OUT = V_OUTmin – 100 mV			15	mV
DC line regulation	On mode, V_OUT = 1.8 V, I_OUT = I_OUTmax			2	mV
Transient load regulation	On mode, V_IN = 3.8 V, I_OUT = 0.1 × I_OUTmax to 0.9 × I_OUTmax in 5 µs		15		mV
	And I_OUT = 0.9 × I_OUTmax to 0.1 × I_OUTmax in 5 µs
Transient line regulation	On mode, I_OUT = I_OUTmax, V_IN = V_INmin + 0.5 V to V_INmin in 30 µs		0.5		mV
	And V_IN = V_INmin to V_INmin + 0.5 V in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, at V_OUT = 0.1 V up to V_OUTmin		100		µs
Turn-on Inrush current			600		mA
Ripple Rejection	V_IN = V_INDC + 100 mV_pp tone, V_INDC+ = 3.8 V, I_OUT = I_OUTmax/2
	f = 217 Hz		70		dB
	f = 50 kHz		40		dB
VDAC internal resistance	LDO off		360		kΩ
Ground current	On mode, I_OUT = 0		60		µA
	On mode, I_OUT = I_OUTmax		1600
	Low-power mode		12
	Off mode			1
VPLL
DC output voltage V_OUT	On and low-power mode, V_IN = V_INmin to V_INmax
	SEL = 11, I_OUT = 0 to I_OUTmax	–3%	2.5	+3%	V
	SEL = 10, I_OUT = 0 to I_OUTmax, default BOOT[1:0 = 00 or 01	–3%	1.8	+3%
	SEL = 01, I_OUT = 0 to I_OUTmax	–3%	1.1	+3%
	SEL = 00, I_OUT = 0 to I_OUTmax	–3%	1.0	+3%
Rated output current I_OUTmax	On mode	50			mA
	Low-power mode	1			mA
Load current limitation (short-circuit protection)	On mode, V_OUT = V_OUTmin – 100 mV	200	400		mA
Dropout voltage V_DO	On mode, V_OUTtyp = 2.5 V, V_DO = V_IN – V_OUT,		100		mV
	V_IN = 2.5 V, I_OUT = I_OUTmax, T = 25°C
DC load regulation	On mode, I_OUT = I_OUTmax to 0			10	mV
DC line regulation	On mode, V_IN = V_INmin to V_INmax at I_OUT = I_OUTmax			1	mV
Transient load regulation	On mode, V_IN = 3.8 V, I_OUT = 0.1 × I_OUTmax to 0.9 × I_OUTmax in 5 µs		9		mV
	And I_OUT = 0.9 × I_OUTmax to 0.1 × I_OUTmax in 5 µs
Transient line regulation	On mode, V_IN = V_INmin + 0.5 V to V_INmin in 30 µs		0.5		mV
	And V_IN = V_INmin to V_INmin + 0.5 V in 30 µs, I_OUT = I_OUTmax/2
Turn-on time	I_OUT = 0, at V_OUT = 0.1 V up to V_OUTmin		100		µs
Turn-on in rush current			300		mA
Ripple rejection	V_IN = V_INDC + 100 mV_pp tone, V_INDC+ = 3.8 V, I_OUT = I_OUTmax/2
	f = 217 Hz		70		dB
	f = 50 kHz		40		dB
VPLL internal resistance	LDO off		535		kΩ
Ground current	On mode, I_OUT = 0		60		µA
	On mode, I_OUT = I_OUTmax		1600
	Low-power mode		12
	Off mode			1

5.22 Timing and Switching Characteristics

5.22.1 Switch-On/-Off Sequences and Timing

Time slot length can be selected to be 0.5 ms or 2 ms through the EEPROM for an OFF-to-ACTIVE transition or through the value programmed in the register DEVCTRL2_REG for a SLEEP-to-ACTIVE transition.

5.22.1.1 BOOT1 = 0, BOOT0 = 0

Table 5-1 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot mode is provided in Figure 5-1.

Table 5-1 Fixed Boot Mode: 00

Register	Bit	Description	TPS65910 Boot 00
VDD1_OP_REG	SEL	VDD1 voltage level selection for boot	1.2 V
VDD1_REG	VGAIN_SEL	VDD1 gain selection, x1 or x2	x1
EEPROM		VDD1 time slot selection	3
DCDCCTRL_REG	VDD1_PSKIP	VDD1 pulse skip mode enable	skip enabled
VDD2_OP_REG/VDD2_SR_REG	SEL	VDD2 voltage level selection for boot	1.1 V
VDD2_REG	VGAIN_SEL	VDD2 Gain selection, x1 or x3	x3
EEPROM		VDD2 time slot selection	2
DCDCCTRL_REG	VDD2_PSKIP	VDD2 pulse skip mode enable	skip enabled
VIO_REG	SEL	VIO voltage selection	1.8 V
EEPROM		VIO time slot selection	1
DCDCCTRL_REG	VIO_PSKIP	VIO pulse skip mode enable	skip enabled
EEPROM		VDD3 time slot	OFF
VDIG1_REG	SEL	LDO voltage selection	1.2 V
EEPROM		LDO time slot	OFF
VDIG2_REG	SEL	LDO voltage selection	1.0 V
EEPROM		LDO time slot	OFF
VDAC_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	5
VPLL_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	4
VAUX1_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	1
VMMC_REG	SEL	LDO voltage selection	3.3 V
EEPROM		LDO time slot	6
VAUX33_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	OFF
VAUX2_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	5
CLK32KOUT pin		CLK32KOUT time slot	7
NRESPWRON pin		NRESPWRON time slot	7 + 1
VRTC_REG	VRTC_OFFMASK	0: VRTC LDO will be in low-power mode during OFF state	Low-power mode
VRTC_REG	VRTC_OFFMASK	1: VRC LDO will be in full-power mode during OFF state	Low-power mode
DEVCTRL_REG	RTC_PWDN	0: RTC in normal power mode	1
DEVCTRL_REG	RTC_PWDN	1: Clock gating of RTC register and logic, low-power mode	1
DEVCTRL_REG	CK32K_CTRL	0: Clock source is crystal/external clock	RC
DEVCTRL_REG	CK32K_CTRL	1: Clock source is internal RC oscillator	RC
DEVCTRL2_REG	TSLOT_LENGTH[0]	Boot sequence time slot duration:	2 ms
		0: 0.5 ms
		1: 2 ms
DEVCTRL2_REG	IT_POL	0: INT1 signal will be active-low	Active-low
DEVCTRL2_REG	IT_POL	1: INT1 signal will be active-high	Active-low
INT_MSK_REG	VMBHI_IT_MSK	0: Device will automatically switch-on at NOSUPPLY to OFF or BACKUP to OFF transition	0: Automatic switch-on from supply insertion
INT_MSK_REG	VMBHI_IT_MSK	1: Startup reason required before switch-on	0: Automatic switch-on from supply insertion
VMBCH_REG	VMBCH_SEL[1:0]	Select threshold for main battery comparator threshold VMBCH.	3 V

Figure 5-1 shows the 00 Boot mode timing characteristics.

Figure 5-1 Boot Mode: BOOT1 = 0, BOOT0 = 0

Table 5-2 lists the 00 Boot mode timing characteristics.

Table 5-2 Boot Mode: BOOT1 = 0, BOOT0 = 0 Timing Characteristics

PARAMETER	TEST CONDITIONS	TYP	UNIT
t_dSON1	PWRHOLD rising edge to VIO, VAUX1 enable delay	66 × t_CK32k = 2060	µs
t_dSON2	VIO to VDD2 enable delay	64 × t_CK32k = 2000	µs
t_dSON3	VDD2 to VDD1 enable delay	64 × t_CK32k = 2000	µs
t_dSON4	VDD1 to VPLL enable delay	64 × t_CK32k = 2000	µs
t_dSON5	VPLL to VDAC,VAUX2 enable delay	64 × t_CK32k = 2000	µs
t_dSON6	VDAC to VMMC enable delay	64 × t_CK32k = 2000	µs
	VMMC to CLK32KOUT rising edge delay	64 × t_CK32k = 2000	µs
t_dSON8	CLK32KOUT to NRESPWRON rising edge delay	64 × t_CK32k = 2000	µs
t_dSONT	Total switch-on delay	16	ms
t_dSOFF1	PWRHOLD falling edge to NRESPWRON falling edge delay	2 × t_CK32k = 62.5	µs
t_dSOFF1B	NRESPWRON falling edge to CLK32KOUT low delay	3 × t_CK32k = 92	µs
t_dSOFF2	PWRHOLD falling edge to supplies and reference disable delay	5 × t_CK32k = 154	µs

Registers default setting: CK32K_CTRL = 1 (32-kHz RC oscillator is used), RTC_PWDN = 1 (RTC domain off), IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on Battery plug), VMBCH_SEL = 11.

5.22.1.2 BOOT1 = 0, BOOT0 = 1

Table 5-3 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot mode is provided in Figure 5-2.

Table 5-3 Fixed Boot Mode: 01

Register	Bit	Description	TPS65910 Boot 01
VDD1_OP_REG	SEL	VDD1 voltage level selection for boot	1.2 V
VDD1_REG	VGAIN_SEL	VDD1 Gain selection, x1 or x2	x1
EEPROM		VDD1 time slot selection	3
DCDCCTRL_REG	VDD1_PSKIP	VDD1 pulse skip mode enable	Skip enabled
VDD2_OP_REG/VDD2_SR_REG	SEL	VDD2 voltage level selection for boot	1.2 V
VDD2_REG	VGAIN_SEL	VDD2 Gain selection, x1 or x3	x1
EEPROM		VDD2 time slot selection	4
DCDCCTRL_REG	VDD2_PSKIP	VDD2 pulse skip mode enable	Skip enabled
VIO_REG	SEL	VIO voltage selection	1.8 V
EEPROM		VIO time slot selection	1
DCDCCTRL_REG	VIO_PSKIP	VIO pulse skip mode enable	Skip enabled
EEPROM		VDD3 time slot	OFF
VDIG1_REG	SEL	LDO voltage selection	1.2 V
EEPROM		LDO time slot	OFF
VDIG2_REG	SEL	LDO voltage selection	1.0 V
EEPROM		LDO time slot	OFF
VDAC_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	OFF
VPLL_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	2
VAUX1_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	OFF
VMMC_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	OFF
VAUX33_REG	SEL	LDO voltage selection	3.3 V
EEPROM		LDO time slot	6
VAUX2_REG	SEL	LDO voltage selection	1.8 V
EEPROM		LDO time slot	5
CLK32KOUT pin		CLK32KOUT time slot	7
NRESPWRON pin		NRESPWRON time slot	7+1
VRTC_REG	VRTC_OFFMASK	0: VRTC LDO will be in low-power mode during OFF state	low-power mode
VRTC_REG	VRTC_OFFMASK	1: VRC LDO will be in full-power mode during OFF state	low-power mode
DEVCTRL_REG	RTC_PWDN	0: RTC in normal power mode	1
DEVCTRL_REG	RTC_PWDN	1: Clock gating of RTC register and logic, low-power mode	1
DEVCTRL_REG	CK32K_CTRL	0: Clock source is crystal/external clock	Crystal
DEVCTRL_REG	CK32K_CTRL	1: Clock source is internal RC oscillator	Crystal
DEVCTRL2_REG	TSLOT_LENGTH[0]	Boot sequence time slot duration:	2 ms
		0: 0.5 ms
		1: 2 ms
DEVCTRL2_REG	IT_POL	0: INT1 signal will be active-low	Active-low
DEVCTRL2_REG	IT_POL	1: INT1 signal will be active-high	Active-low
INT_MSK_REG	VMBHI_IT_MSK	0: Device will automatically switch-on at NOSUPPLY to OFF or BACKUP to OFF transition	0: Automatic switch-on from supply insertion
INT_MSK_REG	VMBHI_IT_MSK	1: Startup reason required before switch-on	0: Automatic switch-on from supply insertion
VMBCH_REG	VMBCH_SEL[1:0]	Select threshold for main battery comparator threshold VMBCH.	3 V

Figure 5-2 shows the 01 Boot mode timing characteristics.

Figure 5-2 Boot Mode: BOOT1 = 0, BOOT0 = 1

Table 5-4 lists the 01 Boot mode timing characteristics.

Table 5-4 Boot Mode: BOOT1 = 0, BOOT0 = 1 Timing Characteristics

PARAMETER	TEST CONDITIONS	TYP	UNIT
t_dSON1	PWRHOLD rising edge to VIO enable delay	66 × t_CK32k = 2060	µs
t_dSON2	VIO to VPLL enable delay	64 × t_CK32k = 2000	µs
t_dSON3	VPLL to VDD1 enable delay	64 × t_CK32k = 2000	µs
t_dSON4	VDD1 to VDD2 enable delay	64 × t_CK32k = 2000	µs
t_dSON5	VDD2 to VAUX2 enable delay	64 × t_CK32k = 2000	µs
t_dSON6	VAUX2 to VAUX33 enable delay	64 × t_CK32k = 2000	µs
t_dSON7	VAUX33 to CLK32KOUT enable delay	64 × t_CK32k = 2000	µs
t_dSON8	CLK32KOUT to NRESPWRON enable delay	64 × t_CK32k = 2000	µs
t_dSONT	Total switch-on delay	16	ms
t_dSOFF1	PWRHOLD falling edge to NRESPWRON falling edge	2 × t_CK32k = 62.5	µs
t_dSOFF1B	NRESPWRON falling edge to CLK32KOUT low delay	3 × t_CK32k = 92	µs
t_dSOFF2	PWRHOLD falling edge to supplies disable delay	5 × t_CK32k = 154	µs

Registers default setting: CK32K_CTRL = 0 (32-kHz quartz or external bypass clock is used), RTC_PWDN = 1 (RTC domain off), IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on battery plug), VMBCH_SEL = 11.

5.22.2 Power Control Timing

5.22.2.1 Device Turn-On/Off With Rising/Falling Input Voltage

Figure 5-3 shows the device turn-on/-off with rising/falling input voltage.

(1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after the switch-on sequence. If none of these devices Power-on enable conditions are set, the supplies will be turned off after t_dOINT1 delay.

Figure 5-3 Device Turn-On/Off with Rising/Falling Input Voltage

5.22.2.2 Device State Control Through PWRON Signal

Figure 5-4 shows the device state control through PWRON signal.

(1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after switch-on sequence, If none of these devices POWER-ON enable condition are set the supplies will be turned off after T_dOINT1 delay.

Figure 5-4 PWRON Turn-On/Turn-Off

Figure 5-5 shows the long-press turn-off timing characteristics.

If the DEV_ON control bit is set to 1 or PWRHOLD is kept high, the device will be turned on again after PWRON long press turn-off and PWRON released.

Figure 5-5 PWRON Long-Press Turn-Off

Table 5-5 lists the power control timing characteristics.

Table 5-5 Power Control Timing Characteristics

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_d32KON: 32-kHz Oscillator turn-on time	BOOT[1:0] = 00, RC oscillator		0.1	2000	ms
	BOOT[1:0] = 01, Quartz oscillator		400
	BOOT[1:0] = 01, Bypass clock		0.1
t_dbVMBHI: VMBHI rising-edge debouncing delay		3 × t_CK32k = 94		4 × t_CK32k = 125	µs
t_dbVMBDCH: Main Battery voltage = VMBDCH threshold to INT1 falling-edge delay		3 × t_CK32k = 94		4 × t_CK32k = 125	s
t_dbVMBLO: Main Battery voltage = VMBLO threshold to NRESPWRON falling-edge delay		3 × t_CK32k = 94		4 × t_CK32k = 125	s
t_dbPWRONF: PWRON falling-edge debouncing delay		500		550	ms
t_dbPWRONR: PWRON rising-edge debouncing delay		3 × t_CK32k= 94		4 × t_CK32k = 125	µs
t_dbPWRHOLD: PWRON rising-edge debouncing delay		2 × t_CK32k = 63		3 × t_CK32k= 94	µs
t_dOINT: INT1 (internal) Power-on pulse duration after PWRON low-level (debounced) event			1		s
t_dONPWHOLD: delay to set high PWRHOLD signal or DEV_ON control bit after NRESPWRON released to keep on the supplies			984		ms
t_dPWRONLP: PWRON long-press delay to interrupt	PWRON falling edge to PWON_LP_IT = 1		6		s
t_dPWRONLPTO: PWRON long-press delay to turn-off	PWRON falling edge to NRESPWRON falling edge		8		s

5.22.2.3 Device SLEEP State Control

Figure 5-6 shows the device SLEEP state control timing characteristics.

Registers programming: VIO_PSKIP = 0, VDD1_PSKIP = 0, VDD1_SETOFF = 1, VDAC_SETOFF = 1, VPLL_SETOFF = 1, VAUX2_KEEPON = 1

Figure 5-6 Device SLEEP State Control

Table 5-6 Device SLEEP State Control Timing Characteristics

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_ACT2SLP	SLEEP falling edge to supply in low power mode (SLEEP resynchronization delay)	2 × t_CK32k = 62		3 × t_CK32k = 94	µs
t_ACT2SLP	SLEEP falling edge to CLK32KOUT low	156	t_ACT2SLP + 3 × t_CK32k	188	µs
t_SLP2ACT	SLEEP rising edge to supply in high power mode	8 × t_CK32k = 250		9 × t_CK32k = 281	µs
t_SLP2ACTCK32K	SLEEP rising edge to CLK32KOUT running	344	t_SLP2ACT + 3 × t_CK32k	375	µs
t_dSLPON1	SLEEP rising edge to time step 1 of the tun-on sequence from SLEEP state	281	t_SLP2ACT + 1 × t_CK32k	312	µs
t_dSLPONST	turn-on sequence step duration, from SLEEP state				µs
	TSLOT_LENGTH[1:0] = 00		0
	TSLOT_LENGTH[1:0] = 01		200
	TSLOT_LENGTH[1:0] = 10		500
	TSLOT_LENGTH[1:0] = 11		2000
t_dSLPONDCDC	VDD1, VDD2 or VIO tun-on delay from tun-on sequence time step		2 × t_CK32k = 62		us

5.22.2.4 Power Supplies State Control Through the SCLSR_EN1 and SDASR_EN2 Signals

Figure 5-7 andFigure 5-8 show the power supplies state control through the SCLSR_EN1 and SDASR_EN2 signals timing characteristics.

Figure 5-7 LDO Type Supplies State Control Through SCLSR_EN1 and SCLSR_EN2

Figure 5-8 VDD1 and VDD2 Supplies State Control Through SCLSR_EN1 and SCLSR_EN2

Table 5-7 Supplies State Control Though SCLSR_EN1 and SCLSR_EN2 Timing Characteristics

PARAMETER	TYP	UNIT
t_dEN: NREPSWON to supply state change delay, SCLSR_EN1 or SCLSR_EN2 driven	0	ms
t_dEN: SCLSR_EN1 or SCLSR_EN2 edge to supply state change delay	1 × t_CK32k = 31	µs
t_dVDDEN: SCLSR_EN1 or SCLSR_EN2 edge to VDD1 or VDD2 DC-DC turn on delay	3 × t_CK32k = 63	µs

5.22.2.5 VDD1 and VDD2 Voltage Control Through SCLSR_EN1 and SDASR_EN2 Signals

Figure 5-9 shows the VDD1 and VDD2 voltage control through the SCLSR_EN1 and SDASR_EN2 signals timing characteristics.

Figure 5-9 VDD1 Supply Voltage Control Though SCLSR_EN1

Table 5-8 VDD1 Supply Voltage Control Through SCLSR_EN1 Timing Characteristics

PARAMETER	TEST CONDITIONS	TYP	UNIT
t_dDVSEN: SCLSR_EN1 or SCLSR_EN2 edge to VDD1 or VDD2 voltage change delay		2 × t_CK32k = 62	µs
t_dDVSENL: VDD1 or VDD2 voltage settling delay	TSTEP[2:0] = 001	32	µs
	TSTEP[2:0] = 011 (default)	0.4/7.5 = 53
	TSTEP[2:0] = 111	160

5.22.2.6 SMPS Switching Synchronization

Figure 5-10 shows the SMPS switching synchronization timing characteristics.

VDD1 or VDD2 switching synchronization is available in PWM mode (VDD1_PSKIP = 0 or VDD2_PSKIP = 0). SMPS external clock (GPIO_CKSYNC) synchronization is available when VIO PWM mode is set (VIO_PSKIP = 0).

Figure 5-10 SMPS Switching Synchronization

Table 5-9 SMPS Switching Synchronization Timing Characteristics

PARAMETER	TEST CONDITIONS	TYP	UNIT
t_dSWIO2SW1: delay from SWIO rising edge to SW1 rising edge	VDD1_PSKIP = 0,		ns
	DCDCCKSYNC[1:0] = 11	160
	DCDCCKSYNC[1:0] = 01	220
t_dSWIO2SW2: delay from SWIO rising edge to SW1 rising edge	VDD2_PSKIP = 0,		ns
	DCDCCKSYNC[1:0] = 11	160
	DCDCCKSYNC[1:0] = 01	290
t_dSWIO2SW3: delay from SWIO rising edge to SW3 rising edge		206	ns