The TPS7B4250-Q1 device is a monolithic, integrated low-dropout voltage tracker. The device is available in a SOT-23 package. The TPS7B4250-Q1 device is designed to supply off-board sensors in an automotive environment. The IC has integrated protection for overload, over temperature, reverse polarity, and output short-circuit to the battery and ground.
A reference voltage applied at the adjust-input pin, ADJ, regulates supply voltages up to VIN = 45 V with high accuracy and loads up to 50 mA.
By setting the adjust/enable input pin, ADJ/EN, to low, the TPS7B4250-Q1 device switches to standby mode which reduces the quiescent current to the minimum value.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7B4250-Q1 | SOT-23 (5) | 2.90 mm × 1.60 mm |
Changes from B Revision (July 2015) to C Revision
Changes from A Revision (November 2013) to B Revision
Changes from * Revision (October 2013) to A Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ADJ/EN | 1 | I | This pin connects to the reference voltage. A low signal disables the IC and a high signal enables the device. Connected the voltage reference directly or with a voltage divider for lower output voltages. To compensate for line influences, TI recommends to place a capacitor close to the IC pins. |
GND | 2 | G | Internally connected to pin 5 |
GND | 5 | G | Internally connected to pin 2 |
VIN | 3 | I | This pin is the device supply. To compensate for line influences, TI recommends to place a capacitor close to the IC pins. |
VOUT | 4 | O | VOUT is an external capacitor that is required between VOUT and GND with respect to the capacitance and ESR requirements given in the Recommended Operating Conditions. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Input voltage, unregulated input, VIN(2)(3) | –20 | 45 | V | ||
Output voltage, regulated output, VOUT | –1 | 22 | V | ||
Adjust input and enable input voltage, ADJ/EN(2)(3) | –0.3 | 22 | V | ||
ADJ Voltage minus input voltage (ADJ–VIN), VIN > 0 V | 7 | V | |||
Operating junction temperature, TJ | –40 | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±4000 | V |
Charged-device model (CDM), per AEC Q100-011 | ±1000 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN | Unregulated input | 4 | 40 | V |
VOUT | regulated output | 1.5 | 18 | V |
ADJ/EN | Adjust input and enable input voltage | 1.5 | 18 | V |
ADJ–VIN | ADJ voltage minus input voltage | 5 | V | |
COUT | Output capacitor requirements(1) | 1 | 50 | µF |
ESRCOUT | Output ESR requirements | 0.001 | 20 | Ω |
TJ | Operating junction temperature | –40 | 150 | °C |
THERMAL METRIC(2)(1) | TPS7B4250-Q1 | UNIT | |
---|---|---|---|
DBV (SOT-23) | |||
5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 171.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 81.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 31.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 4.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 31.2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VUVLO | VIN undervoltage detection | Ramp up VI until the output turns on, VADJ = 1.5 V | 3.65 | V | ||
Ramp down VI until the output turns off, VADJ = 1.5 V | 3 | |||||
ΔVO | Output-voltage tracking accuracy | IO = 100 µA to 1 mA, VI = 4 V to 40 V, 1.5 V < VADJ < VI – 0.3 V | –4 | 4 | mV | |
IO = 1 mA to 50 mA, VI = 4 V to 40 V, 1.5 V < VADJ < VI – 1.5 V | –5 | 5 | ||||
ΔVO(ΔIL) | Load regulation steady-state | IO = 1 mA to 30 mA | 4 | mV | ||
ΔVO(ΔVI) | Line regulation steady-state | IO = 10 mA, VI = 6 V to 40 V | 3 | mV | ||
PSRR | Power-supply ripple rejection | Frequency = 100 Hz, Vrip = 0.5 VPP, IO = 5 mA, CO = 2.2 µF | 60 | dB | ||
Vdropout | Dropout voltage, Vdropout = VI – VQ | IO = 10 mA, VI ≥ 4 V(1) | 150 | 265 | mV | |
IO = 50 mA, VI ≥ 4 V(1) | 550 | 1000 | ||||
IL | Output-current limitation | VO short to GND | 100 | 500 | mA | |
IR | Reverse current at VIN | VI = 0 V, VO = 20 V, VADJ = 5 V | –5 | 0 | µA | |
IRN1 | Reverse current at negative input voltage | VI = –20 V, VO = 0 V, VADJ = 5 V | –5 | 0 | µA | |
IRN2 | VI = –20 V, VO = 20 V, VADJ = 5 V | –5 | 0 | |||
TSD | Thermal shutdown temperature | TJ increasing because of power dissipation generated by the IC | 175 | °C | ||
IQ | Current consumption | VADJ < 0.8 V, TA ≤ 85°C(2) | 7.5 | 15 | µA | |
VADJ < 0.8 V, TA ≤ 125°C | 20 | |||||
IO = 0.5 mA, VADJ = 5 V | 40 | 90 | ||||
IO = 30 mA, VADJ = 5 V | 150 | 350 | ||||
IADJ | Adjust-input and enable-input current | VADJ = 5 V | 1 | µA | ||
VADJ,low | Adjust and enable low signal valid | VO = 0 V | 0.8 | V | ||
VADJ,high | Adjust and enable high signal valid | |VO – VADJ| < 5 mV | 1.5 | 18 | V |
VI = VADJ = 4 V | IO = 10 mA | |
VI = 13.5 V | VADJ = 5 V | |
VI = VADJ = 4 V | ||
VI = 13.5 V | VADJ = 5 V | IO = 1 mA, 50 mA |
The TPS7B4250-Q1 device is a monolithic integrated low-dropout voltage tracker with ultra-low tracking tolerance. Several types of protection circuits are also integrated in the device such as output current limitation, reverse polarity protection, and thermal shutdown in case of over temperature.
VOUT is the regulated output based on the reference voltage. The output has current limitation. During initial power up, the regulator has an incorporated soft start to control the initial current through the pass element.
The device has an internally-fixed undervoltage shutdown threshold. Undervoltage shutdown activates when the input voltage on VIN drops below UVLO. This activation ensures the regulator is not latched into an unknown state during low input supply voltage. If the input voltage has a negative transient that drops below the UVLO threshold and recovers, the regulator shuts down and powers up similar to a standard power-up sequence when the input voltage is above the required levels.
Thermal protection disables the output when the junction temperature rises to approximately 175°C which allows the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.
The internal protection circuitry of the TPS7B4250-Q1 device has been designed to protect against overload conditions. The circuitry was not intended to replace proper heat-sinking. Continuously running the TPS7B4250-Q1 device into thermal shutdown degrades device reliability.
The TPS7B4250-Q1 device survives a short to battery when the output is shorted to the battery as shown in Figure 13. No damage occurs to the device. A short to the battery can also occur when the device is powered by an isolated supply at a lower voltage as shown in Figure 14. In this case the TPS7B4250-Q1 supply input voltage is set at 7 V when a short to battery (14 V typical) occurs on VOUT which typically runs at 5 V. The continuous reverse current flows out through VIN is less than 5 µA.
By pulling the reference voltage of the device below 0.8 V, the IC disables and enters a sleep state where the device draws 7.5 µA (typical) from the power supply. In a real application, the reference voltage is generally sourced from another LDO voltage rail. A case where the device must be disabled without a shutdown of the reference voltage can occur. In such case, the device can be configured as shown in Figure 15. The TPS7A6650-Q1 device is a 150-mA LDO with ultra-low quiescent current that is used as a reference voltage to the TPS7B4250-Q1 device and also as a power supply to the ADC. In a configuration as shown in Figure 15, the status of the device is controlled by an MCU I/O.
The device operates with input voltages above 4 V. The maximum UVLO voltage is 3 V and operates at input voltage above 4 V. The device can also operate at lower input voltages; no minimum UVLO voltage is specified. At input voltages below the actual UVLO voltage, the device does not operate.
The rising-edge threshold voltage of the ADJ/EN pin is 1.5 V (maximum). When the EN pin is held above that voltage and the input voltage is above the 4 V, the device becomes active. The enable falling edge is 0.8 V (minimum). When the EN pin is held below that voltage the device is disabled, the IC quiescent current is reduced in this state.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Based on the end-application, different values of external components can be used. An application can require a larger output capacitor during fast load steps to prevent a reset from occurring. TI recommends a low ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response.
Figure 16 show typical application circuit for the TPS7B4250-Q1 device.
For this design example, use the parameters listed in Table 1.
DESIGN PARAMETER | EXAMPLE VALUES |
---|---|
Input voltage | 4 to 40 V |
ADJ reference voltage | 1.5 to 18 V |
Output voltage | 1.5 to 18 V |
Output current rating | 50 mA |
Output capacitor range | 1 µF to 50 µF |
Output capacitor ESR range | 1 mΩ to 20 Ω |
To begin the design process, determine the following:
An input capacitor, CI, is recommended to buffer line influences. Connect the capacitors close to the IC pins.
The output capacitor for the TPS7B4250-Q1 device is required for stability. Without the output capacitor, the regulator oscillates. The actual size and type of the output capacitor can vary based on the application load and temperature range. The effective series resistance (ESR) of the capacitor is also a factor in the IC stability. The worst case is determined at the minimum ambient temperature and maximum load expected. To ensure stability of TPS7B4250-Q1 device, the device requires an output capacitor between 1 µF and 50 µF with an ESR range between 0.001 Ω and 20 Ω that can cover most types of capacitor ESR variation under the recommend operating conditions. As a result, the output capacitor selection is flexible.
The capacitor must also be rated at all ambient temperature expected in the system. To maintain regulator stability down to –40°C, use a capacitor rated at that temperature.
VI = 12 V | VADJ = 5 V | |
VI = 12 V | VADJ = 5 V | |