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TPSM8287Bxx 2.7V to 6V Input, 15A, 20A, 25A, and 30A, Parallelable, Step-Down Power Module With I2C Interface and Remote Sense in a MagPack Package
SLVSI15
March 2025
TPSM8287B30
ADVANCE INFORMATION
CONTENTS
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TPSM8287Bxx 2.7V to 6V Input, 15A, 20A, 25A, and 30A, Parallelable, Step-Down Power Module With I2C Interface and Remote Sense in a MagPack Package
1
1
Features
2
Applications
3
Description
4
Device Options
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Interface Timing Requirements
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Fixed-Frequency DCS-Control Topology
7.3.2
Forced PWM and Power Save Modes
7.3.3
Precise Enable
7.3.4
Start-Up
7.3.5
Output Voltage Setting
7.3.5.1
Output Voltage Setpoint
7.3.5.2
Output Voltage Range
7.3.5.3
Non-Default Output Voltage Setpoint
7.3.5.4
Dynamic Voltage Scaling (DVS)
7.3.5.5
Droop Compensation
7.3.6
Compensation (COMP)
7.3.7
Mode Selection / Clock Synchronization (MODE/SYNC)
7.3.8
Spread Spectrum Clocking (SSC)
7.3.9
Output Discharge
7.3.10
Undervoltage Lockout (UVLO)
7.3.11
Overvoltage Lockout (OVLO)
7.3.12
Overcurrent Protection
7.3.12.1
Cycle-by-Cycle Current Limiting
7.3.12.2
Hiccup Mode
7.3.12.3
Current-Limit Mode
7.3.13
Power Good (PG)
7.3.13.1
Power-Good Standalone, Primary Device Behavior
7.3.13.2
Power-Good Secondary Device Behavior
7.3.14
Remote Sense
7.3.15
Thermal Warning and Shutdown
7.3.16
Stacked Operation
7.4
Device Functional Modes
7.4.1
Power-On Reset (POR)
7.4.2
Undervoltage Lockout
7.4.3
Standby
7.4.4
On
7.5
Programming
7.5.1
Serial Interface Description
7.5.2
Standard-, Fast-, Fast-Mode Plus Protocol
7.5.3
I2C HS-Mode Protocol
7.5.4
I2C Update Sequence
7.5.5
I2C Register Reset
8
Device Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Selecting the Input Capacitors
9.2.2.2
Selecting the Target Loop Bandwidth
9.2.2.3
Selecting the Compensation Resistor
9.2.2.4
Selecting the Output Capacitors
9.2.2.5
Selecting the Compensation Capacitor, CComp1
9.2.2.6
Selecting the Compensation Capacitor, CComp2
9.2.3
Application Curves
9.3
Typical Application Using Two TPSM8287B30x in Parallel Operation
9.3.1
Design Requirements
9.3.2
Detailed Design Procedure
9.3.2.1
Selecting the Input Capacitors
9.3.2.2
Selecting the Target Loop Bandwidth
9.3.2.3
Selecting the Compensation Resistor
9.3.2.4
Selecting the Output Capacitors
9.3.2.5
Selecting the Compensation Capacitor, CComp1
9.3.2.6
Selecting the Compensation Capacitor, CComp2
9.3.3
Application Curves
9.4
Power Supply Recommendations
9.5
Layout
9.5.1
Layout Guidelines
9.5.2
Layout Example
9.5.2.1
Thermal Considerations
10
Device and Documentation Support
10.1
Device Support
10.1.1
Third-Party Products Disclaimer
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
Support Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Tape and Reel Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
VCH|37
Thermal pad, mechanical data (Package|Pins)
Orderable Information
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Data Sheet
TPSM8287Bxx 2.7V to 6V Input, 15A, 20A, 25A, and 30A, Parallelable, Step-Down Power Module With I
2
C Interface and Remote Sense in a
MagPack
Package
1
Features
±0.8% output voltage accuracy
Differential remote sensing
Parallelable for multiphase operation
Start-up output voltage and I
2
C addresses selectable through VSETx pins:
0.4V to 0.775V in 25mV steps
0.8V to 1.55V in 50mV steps
Output voltage I
2
C adjustable in 1.25mV steps
Adjustable external compensation for wide output capacitor range and optimized transient response
Designed for low EMI requirements
MagPack technology shields inductor and IC
No bond wire package
Internal input and output capacitors
Simplified layout through parallel input path
Optional synchronization to external clock or spread-spectrum operation
Optional droop compensation through I
2
C
Power save mode or forced PWM operation
Precise enable input threshold
Power-good output with window comparator
Active output discharge
Excellent thermal performance
–40°C to 125°C operating temperature range
3.75mm × 8.0mm QFN package with 0.5mm pitch
66mm
2
solution size
2
Applications
FPGA, ASIC, and SoC digital core supply
Optical networks
Test and measurement equipment
Sensors, imaging, and radar
