UCC256304 Ultra Wide VIN LLC Resonant Controller Enabling Low Standby Power

7.3.1 Hybrid Hysteretic Control

UCC256304 uses a novel control scheme – Hybrid Hysteretic Control (HHC) - to achieve best in class line and load transient performance. The control method makes the compensator very easy to design. The control method also makes light load management easier and more efficient. Improved line transient enables lower bulk capacitor/output capacitor value and saves system cost.

HHC is a control method which combines traditional frequency control and charge control – It is charge control with added frequency compensation ramp. Comparing with traditional frequency control, it changes the power stage transfer function from a 2nd order system to a 1st order system, so that it is very easy to compensate. The control effort is directly related to input current, so the line and load transients are best in class. Comparing with charge control, the hybrid hysteretic control avoids unstable condition by adding in a frequency compensation ramp. The frequency compensation makes the system always stable, and makes the output impedance lower as well. Lower output impedance makes the transient performance better than charge control.

In summary, the problems solved by HHC are:

• Help LLC converters achieve best in class load transient and line transient
• Changes the small-signal transfer function to a 1st order system which is very easy to compensate, and can achieve very high bandwidth
• Inherently stable via frequency compensation
• Makes burst mode control high efficiency optimization much easier

Figure 28 shows the HHC implementation in UCC256304: a capacitor divider (C1 and C2) and two well matched controlled current source.

Figure 28. UCC256304 HHC Implementation

The resonant capacitor voltage is divided down by the capacitor divider formed by C1 and C2. The current sources are controlled by the gate drive signals. When high side switch is on, turn on the upper current source to inject a constant current into the capacitor divider; when low side switch is on, turn on the lower current source to pull the same amount of constant current outside of the capacitor divider. The two current sources add a triangular compensation ramp to the V_CR node. The current sources are supplied by a reference voltage V_ref. This voltage needs to be equal to or larger than twice of the common mode voltage V_CM. The divided resonant capacitor voltage and the compensation ramp voltage are then added together to get VCR node voltage. If the frequency compensation ramp dominates, the VCR node voltage will look like a triangular waveform, and the control will be similar to direct frequency control. If the resonant capacitor voltage dominates, the shape of the VCR node voltage will look like the actual resonant capacitor voltage, and the control will be similar to charge control. This is why the control method is called “hybrid” and the compensation ramp is called frequency compensation.

This set up has an inherent negative feedback to keep the high side and low side on time balanced, and also keep the common mode voltage at V_CR node at V_CM.

There are two input signals needed for the new control scheme: V_CR and V_COMP. V_CR is the sum of the scaled down version of the resonant capacitor voltage and the frequency compensation ramp. V_COMP is the voltage loop compensator output. The waveform below shows how the high-side and low-side switches are controlled based on VCR and V_COMP. The common mode voltage of VCR is VCM.

Figure 29. HHC Gate On/Off Control Principle

Based on V_COMP and VCM (3 V), two thresholds: Vthh and Vthl are created.

Equation 1.

Equation 2.

The VCR voltage is compared with the two thresholds. When VCR > Vthh, turn off high side switch; when VCR < Vthl, turn off low side switch. HO and LO turn on edges are controlled by adaptive dead time circuit.

7.3.2 Regulated 12-V Supply

RVCC pin is the regulated 12-V supply which can supply up to 100-mA current. The regulated rail is used to supply the PFC, and LLC gate driver. RVCC has under voltage lock out (UVLO) function. If during normal operation, RVCC voltage is less than RVCCUVLO threshold. It is treated as a fault and the system will enter FAULT state. Details about the FAULT handling will be discussed in the section.

7.3.3 Feedback Chain

Control of output voltage is provided by a voltage regulator circuit located on the secondary side of the isolation barrier. The demand signal from the secondary regulator circuit is transferred across the isolation barrier using an opto-coupler and is fed into the FB pin on UCC256304. This section discusses about the whole feedback chain.

The feedback chain has the following functions:

• Optocoupler feedback signal input and bias
• System external shut down
• Soft start function selection by a pick lower block
• Burst mode selection by a pick higher block
• Convert single ended feedback demand to two thresholds V_thh and V_thl; and V_CR comparison with the thresholds and the common mode voltage V_CM

Figure 30. Feedback Chain Block Diagram

The timing diagram below shows the FB chain waveforms. The sequence is normal soft start followed by a ZCS event, and load step into burst mode, and then come out of burst mode.

Figure 31. Feedback Chain Timing Diagram

7.3.4 Optocoupler Feedback Signal Input and Bias

The secondary regulator circuit and optocoupler feedback circuit all add directly to the no load power consumed by the system. To achieve very low no load power it is necessary to drive the optocoupler in a low current mode.

As shown in Figure 31, a constant current source IFB is generated out of VCC voltage and connected to FB pin. A resistor RFB is also connected to this current source with a PMOS in series. During normal operation, the PMOS is always on. The PMOS limits the maximum voltage on the FBreplica.

Equation 3.

From this equation, when I_opto increases, I_RFB will decrease, making FBreplica decrease. In this way, the control effort is inverted. This circuit can also limit the optocoupler maximum current to be I_FB. A conventional way to bias the optocoupler is using a pull up resistor on the collector of the optocoupler output. To reduce the power consumption, the pull up resistor needs to be big, which will limit the loop bandwidth. For the bias current method used in UCC256304, the optocoupler current is limited and there is no loop bandwidth issue.

7.3.5 System External Shut Down

This function provides a way to shut down the system by an external signal. When the FBreplica is less than the burst mode threshold, stop LLC switching. When FBLessThanBMT is true for more than 200 ms, go to JFET OFF state and try to re-start. Before LLC starts switching, the system has to make sure that FBLessThanBMT is not true. If FBreplica is constantly held low by an external signal, the system will not start again.

This function can be used for system on/off control or any other fault shut down which isn’t included in UCC256304. To implement this function, an external biased optocoupler is needed. The schematic below is an example of such implementation.

Figure 32. External Disable Example Circuit

7.3.6 Pick Lower Block and Soft Start Multiplexer

This part of the circuit consists of 3 elements:

• A pick lower block
• A MUX which selects AVDD or SS signal as the second input to the pick lower block
• A SS control block which handles the charge and discharge of the SS capacitor in cause of a ZCS fault

The pick lower block has two inputs. The first input is FBreplica. The second input is selected between AVDD and SS pin voltage. The other output of the block is the lower of the two inputs.

The MUX selects between SS and AVDD. The selection is based on SSEnd (soft start end) signal, which is an output of the SS Ctrl block. SSEnd is high when SS is higher than FBreplica, and soft start process has been initiated by the state machine, and there is no ZCS condition. Switching to AVDD after soft start has ended helps make sure that during non-soft start or non-ZCS fault condition, FBreplica signal is always sent through the pick lower block. It also releases the SS pin to do the other function – light load threshold programming.

The SS control block handles the charge and discharge of the SS capacitor in cause of a ZCS fault. It reset the SSEnd signal when ZCS happens, so the effect of pulling down on SS pin to increase the switching frequency can pass through the pick lower block. The relationship of the SS control block inputs and outputs is the following:

Equation 4.

Equation 5.

7.3.7 Pick Higher Block and Burst Mode Multiplexer

The output of the pick lower block goes into a pick higher block, which selects the higher of the pick lower block output and the burst mode threshold setting.

The burst mode multiplexer selects between BMT and ground. During soft start, the multiplexer selects ground. The startup process is open loop and controlled by the soft start ramp. Burst mode is not enabled during soft start phase.

After soft start, the higher of the two inputs are sent to the differential amplifier. The other output is a comparator output FBLessThanBMT. It is sent to the waveform generator state machine to control burst mode and system external shut down.

7.3.8 VCR Comparators

The output of the pick higher block is sent to a differential amplifier to convert the signal to two thresholds symmetrical to Vcm. The difference between the two thresholds Vthh and Vthl equals the input amplitude. The VCR pin voltage is then compared with Vthh, Vthl, and Vcm. The results are sent to the waveform generator.

7.3.9 Resonant Capacitor Voltage Sensing

The resonant capacitor voltage sense pin senses the resonant capacitor voltage through a capacitor divider. Inside the device, two well matched, controlled current sources are connected to VCR pin to generate the frequency compensation ramp. The on/off control signals in of the two current sources come from the waveform generator block.

During waveform generator IDLE state or before startup, short VCR node to Vcm. This action will help reduce the startup peak current, and help VCR voltage to settle down quickly during burst mode.

Figure 33. VCR Block Diagram

The ramp current on/off sequence is shown in Figure 34. The ramp current is on all the time. It changes direction at the falling edge of high side on or low side on signal.

Figure 34. VCR Compensation Ramp Current On/Off

On VCR pin, a capacitor divider is used to mix the resonant capacitor waveform and the compensation ramp waveform. Adjusting the size of the external capacitors can change the contribution of charge control and direct frequency control. Assume the divided down version of the resonant capacitor voltage by the capacitor divider is V_div, the compensation ramp current resulted voltage on VCR pin is V_ramp. If V_div is much larger than V_ramp, the control method is similar to charge control, in which the control effort is proportional to the input charge of one switching cycle. If V_ramp is much larger than V_div, the control method is similar to direct frequency control, in which the control effort is proportional to the switching frequency. The most optimal transient response can be achieved by adjusting the ratio between V_div and V_ramp.

7.3.10 Resonant Current Sensing

The ISNS pin is connected to the resonant capacitor using a high voltage capacitor. The capacitor CISNS and the resistor RISNS form a differentiator. The resonant capacitor voltage is differentiated to get the resonant current. The differentiated signal is AC and goes both positive and negative. In order to sense the zero crossing, the signal is level shifted using an op amp adder. IPolarity comparator detects the direction of the resonant current. The digital state machine implements a blanking time on IPolarity – IPolarity edges during the first 400ns of dead time are ignored.

OCP2 and OCP3 thresholds are based on average input current. To get the average input current, the differentiator output is multiplexed with the high side switch on signal HSON: when HS is on, the MUX output is the differentiator output; when HS is off, the MUX output is 0. The MUX output is then averaged using a low pass filter. The output of the filter is the sensed average input current. Note that the MUX needs to pass through both positive and negative voltages. OCP2 and OCP3 faults have a 2ms and 50ms timer respectively. Only when the OCP2/OCP3 comparators output high for continuous 2ms or 50ms, the faults will be activated.

OCP1 threshold is set on the peak resonant current. The voltage on the ISNS pin gets compared to OCP1 threshold OCP1Th directly. The peak resonant current is checked once per cycle on the positive half cycle. OCP1 fault is only activated when there are 4 consecutive cycles of OCP1 event detected. During start up, the OCP1 comparator output of the first 15 cycles are ignored.

Figure 35. ISNS Block Diagram

7.3.11 Bulk Voltage Sensing

The BLK pin is used to sense the LLC DC input voltage (bulk voltage) level. The comparators on BLK pin set the following thresholds:

• Bulk voltage level when LLC starts switching – BLKStartTh
• Bulk voltage level when LLC stops switching – BLKStopTh
• Bulk voltage level when bulk over voltage fault is generated – BLKOVRiseTh
• Bulk voltage level when bulk over voltage fault is cleared – BLKOVFallTh

BLKOV signal is generated by one comparator with two thresholds selected by a MUX. This is to create necessary hysteresis for the BLKOV fault. The BLKSns signal is buffered and sent to burst mode threshold generation block to implement the adaptive burst mode threshold.

Figure 36 shows the block diagram of the BLK pin.

Figure 36. VCR Compensation Ramp Current On/Off

In UCC256304, the BLKOVRiseTh threshold is intentionally made to be much larger than BLKStartTh. This enables the LLC controller to accommodate a very wide DC input voltage range while still maintaining a suitable BLKStopTh. For example, if a startup threshold of 120V is desired, then the BLK resistor divider ratio, k_BLK, can be calculated as

Equation 6.

For the same BLK resistor divider ratio, the bulk stop voltage is

Equation 7.

An over voltage condition occurs when the bulk voltage is greater than or equal to V_OVRise

Equation 8.

The over voltage condition is cleared when the bulk voltage falls below V_OVFall

Equation 9.

This wide DC input range offers a number of system level benefits. When UCC256304 is paired with a PFC stage, the LLC converter is able to startup and enter a low power standby mode without the need to enable the PFC. In addition, the wide DC input range enables AC/DC systems to be compatible with an extensive range of common AC Inputs

Figure 37. Timing Diagram of BLK Operations

7.3.12 Output Voltage Sensing

The output voltage is sensed through the bias winding (BW) voltage sense pin. The sensed output voltage is compared with a fixed threshold to generate output OVP fault. The block diagram of the bias winding voltage sense block is shown below.

Figure 38. Bias Winding Sensing Block Diagram

The bias winding sense block consists of an inverting op amp to flip the BW signal. The flipped BW signal is then peak detected and sampled at low side turn off edge. The sampled voltage represents the output voltage during this cycle. The S/H output is them compared with OVP comparator. Shown below is the timing diagram of the BW sense block.

Figure 39. Timing Diagram of BW Sense Block

7.3.13 High Voltage Gate Driver

The low-side gate driver output is LO. The gate driver is supplied by the 12-V RVCC rail.

The high-side driver module consists of three physical device pins. HB and HS form the positive and negative rails, respectively, of the high-side driver, and HO connects to the gate of the upper half-bridge MOSFET.

During periods when the lower half-bridge MOSFET is conducting, HS is shorted to GND via the conducting lower MOSFET. At this time power for the high side driver is obtained from RVCC via high voltage diode DBOOT, and capacitor CBOOT is charged to RVCC minis the forward drop on the diode.

During periods when the upper half-bridge MOSFET is conducting, HS is connected the LLC input voltage rail. At this time the HV diode is reverse biased and the high side driver is powered by charge stored in CBOOT.

The slew on HS pin is detected for adaptive dead time adjustment. The next gate is only turned on when the slew on HS pin is finished.

Both the high-side and low side gate drivers have under voltage lock out (UVLO) protection. The low side gate driver UVLO is implemented on RVCC; the high side gate driver UVLO is implemented on (HB - HS) voltage.

When operating at light load, UCC256304 enters burst mode. During the burst off period, the gate driver enters low power mode to reduce power consumption.

The block diagram of the gate driver is shown in Figure 40.

Figure 40. Gate Driver Block Diagram

7.3.14 Protections

7.3.14.1 ZCS Region Prevention

Capacitive region is an LLC operation region in which the voltage gain increases when the switching frequency increases. It is also called ZCS region. Capacitive mode operation should be avoided for two reasons:

• The feedback loop becomes positive feedback in capacitive region
• The MOSFET may be damaged because of body diode reverse recovery

To make sure that capacitive region operation does not happen, we need to first rely on the slew done signal. If there is a slew done signal detected, it suggests that the opposite body diode must not be conducting and to turn on the next FET. If there is no slew detected, IPolarity signal is used. The next gate will be turned on at the next IPolarity flip event. The IPolarity flip indicates that the capacitive operation cycle has already passed. The resonant current reverses the direction and begins to discharge the switch node. When the capacitive operation cycle has passed, the system enters a high frequency oscillation stage, where the oscillation frequency is determined by the parasitic elements in the circuit. In this stage, the body diode is no longer conducting and it is allowed to turn on the next gate.

However, in the high frequency oscillation stage, the resonant current may be so small that the IPolarity detection is missed. In this case, the next gate will be turned on by maximum dead time timer expiration.

In addition to preventing the next gate from turning on when the opposite body diode is conducting, the switching frequency is forced to ramp up until there is a cycle with no capacitive region operation detected

The capacitive region detection is done by checking the resonant current polarity at HSON or LSON falling edge. If the resonant current is positive at LSON falling edge, or negative at HSON falling edge, the ZCS signal in the waveform generator is turned high. The ZCS signal keeps high until there is a half cycle without capacitive region operation happens.

The force ramping up of the switching frequency is done by pull the SS pin down by a resistor to ground. Details will be discussed in SS pin section.

Below is the flow chart of capacitive region prevention algorithm:

Figure 41. Gate Driver Block Diagram

Figure 42. Timing Diagram of a ZCS Event

7.4.1 Burst Mode Control

The efficiency of an LLC converter power stage drops rapidly with falling output power. To maintain reasonable light load efficiency it is necessary to operate the LLC converter in burst mode. In this mode the LLC converter operates at relatively high power for a short burst period and then all switching is stopped for a space period. During the Burst period excess charge is transferred to and stored in the output capacitor. During the Space period this stored charge is used to supply the load current. Providing an effective light-load scheme is a particular problem for an LLC controller that is located on the primary side of the isolation barrier. This is because the feedback demand signal (V_COMP) is mainly a function of input/output voltage ratio and only loosely related to load current. The normal method of placing a couple of thresholds in the V_COMP voltage window to switch OFF and ON the LLC converter does not work effectively. Another issue with the conventional method is that when burst on, the switching pulses are determined by V_COMP, which is usually at initial burst on, and decays as the output voltage rises. The resulting inductor current will be big at first and then decays. This is not optimal because the big current at first may create mechanical vibration. The high switching frequency afterwards may cause two much switching loss.

For an advanced burst mode, the following features are desired:

• The power delivered by each burst should be relatively constant for a certain load.
• The Burst power is set high enough to provide reasonable LLC converter efficiency and low enough to avoid acoustic noise and excessive output voltage ripple.
• When burst on, the average capacitor voltage should settle to V_IN/2 as fast as possible for best efficiency.
• The switching frequency or burst power level of each burst pulse should be optimized for efficient operation.
• The burst pattern of each burst should be relatively constant.
• There should be no audible noise.
• Burst mode performance should be consistent across input voltage range.

The HHC method makes the control of the burst mode very straight forward. The block diagram is a functionally accurate description of the burst mode control method in UCC256304.

Figure 43. Burst Mode Control Block Diagram

The control effort is selected between the higher of the two signals: 1) the voltage loop compensator output (V_COMP) or 2) the Burst Mode Threshold level (BMT). When V_COMP goes below BMT, continue switching for a fixed number of switching cycles, then stop. Always switch while COMP is higher than BMT. If soft start isn’t done yet, send the COMP (controlled by soft start ramp). BMT is programmable and adaptively changed with input voltage. The last pulse of each burst on period is turned off when the resonant capacitor voltage equals V_IN/2. In HHC method, this is approximately equivalent to VCR node voltage equals the common mode voltage VCM. This operation keeps the resonant capacitor voltage to about V_IN/2 for each burst off period, thus enabling the burst pattern to settle as soon as possible during burst on period.

7.4.2 High Voltage Start-Up

UCC256304 uses a self bias start up scheme, thus eliminating the need of a separate auxiliary flyback power stage. When AC is first plugged in, PFC and LLC are both off. HV pin JFET will be enabled and will start to deliver current from a source connected to the HV pin to the VCC capacitor. Once the VCC pin voltage exceeds its VCCStartSwitching threshold, the current source will be turned off and RVCC will be enabled to turn on the PFC. When PFC output voltage reaches a certain level, LLC is turned on. When LLC is operating and the output voltage is established, the bias winding will supply current for both the PFC and the LLC controller devicess.

7.4.3 X-Capacitor Discharge

X-capacitors used in EMC filters on the AC side of the diode bridge rectifier must have means to allow them to discharge to a reasonable voltage within certain time, this is to ensure that voltage does not remain present on the pins of the main cord indefinitely.

Typically explicit discharge resistors are provided in parallel with the capacitors to provide this discharge path, but these resistors then lead to fixed standing power loss as long as the power supply is connected to AC, and can be significant in the context of achieving very low standby power.

For every 100 nF of capacitance, a maximum bleed resistor of 10 MΩ must be added in parallel. For a typical 60-W to 100-W power supply with a typical capacitance of 330 nF, this requires 3 MΩ of discharge resistance. At nominal high line 230 V, these resistors dissipate 17.63 mW of standing power loss. Thus it is necessary to find alternative ways to discharge the X-capacitors using switched discharge paths, which avoid the static standing loss.

There are several standards about X-capacitor discharge. IEC60950 and IEC60065 requires that the discharge time constant is less than 1s; IEC62368 requires that after 2 seconds of AC unplug, the remaining voltage on the x-capacitor is less than 60 V (for 300 nF or more capacitance). UCC256304 uses an active discharge scheme to support the fast discharge of up to 5-μF X-capacitor.

To meet the requirements of the standards, AC disconnect event should be detected. UCC256304 detects AC disconnect by monitoring the AC zero crossings through HV pin. When AC is present, there will be two AC zero crossings in one line cycle. When AC is disconnected, there will be no zero crossings for a long time. See Figure 44 shows the rectified AC waveform. In the figure, the AC is disconnected at the peak of the last half AC cycle. In reality, it can be disconnected anywhere in one switching cycle.

Figure 44. AC Disconnect Waveform

To detect the zero crossings reliably as well as save power consumption, a stair case test current is generated every 700 ms. When there are 4 zero crossings missing in a row at the highest test current setting, AC disconnect is confirmed and the IXCapDischarge current source is enabled. The waveform below shows the stair case current waveform:

Figure 45. Staircase Test Current for X-Capacitor Discharge

The test current is required for reliable AC zero crossing sensing. In short, this is because the leakage current in the AC bridge rectifier diodes will affect zero crossing detection at very light load. The added test current on HV pin will overcome the leakage current and make sure that AC zero crossing is detected on HV pin. If one zero crossing is detected during any test current stage, it means that AC is not disconnected. The test current will shut off immediately and the system goes to the 700-ms no test current stage.

Figure 46. Different Staircase Current Waveforms

Figure 46 shows different staircase current waveforms. The last waveform shows the AC disconnect is detected and x-cap discharge current is enabled. The x-cap discharge current is enabled until 350 ms has passed. AC zero crossing function is available in all operation modes and available all the time. Figure 47 shows the flow chart of AC zero crossing detection and X-capacitor discharge.

The discharge current IXCapDischarge is created by turning on the JFET and enable a current source from JFET source to GND. The reason to discharge to GND rather than discharge to VCC is to prevent VCC from reaching VCCStartSwitching. When AC is unplugged right before an OVP event, the voltage on the VCC is close to reaching VCCStartSwitching.

In LATCH state, the JFET is already on and acts as a pass element for the VCC regulation loop. The switch between the JFET source terminal and VCC pin is closed. If X-cap discharge current source is enabled without disconnect the JFET from the VCC pin, the discharge current has to discharge VCC voltage first, which requires a large amount of current to stay on for a long time. To avoid this issue, in LATCH state, the JFET is disconnected from VCC first. When the discharge phase is finished, turn the switch between JFET and VCC back on. Shown below is the circuit diagram and procedures of x-cap discharge in LATCH state.

Figure 47. AC ZCD and X-capacitor Discharge Flow Chart

7.4.4 Soft-Start and Burst-Mode Threshold

The soft-start programming and burst mode threshold programming are multiplexed on one pin – LL/SS. In addition, when ZCS region operation happens, this pin is pulled down to ground through a resistor to increase the switching frequency.

An internal constant current source charges the soft start capacitor to generate the soft-start command. Soft start period starts right after charge boot stage is done, and ends when FBreplica becomes lower than SS pin voltage.

After soft start is done, the SS voltage is replaced by AVDD to send to the FB chain. The LL/SS pin is then used to generate the burst mode threshold. In UCC256304 we try to maintain the same burst mode power level over the input voltage range. This is done by adaptively changing the burst mode threshold with sensed BLK voltage.

The programming resistors output provide two degrees of freedom, to set the burst mode threshold, as well as how the threshold changes with BLK voltage. When programmed correctly, the power stage will always enter burst mode at a certain output current level, making the system much easier to optimize.

Figure 48. LL/SS Block Diagram

7.4.5 System States and Faults State Machine

Below is an overview of the system states sequence:

The state transition diagram starts from the un-powered condition of UCC256304. As soon as the system is plugged in, HV pin JFET will be enabled and will start to deliver current from a source connected to the HV pin to the VCC capacitor. Once the VCC pin voltage exceeds its VCCStartSwitching threshold, system state will change to JFETOFF. When PFC output voltage reaches a certain level, LLC is turned on. Before LLC starts running, the LO pin is kept high to pull the HS node of the LLC bridge low, thus allowing the capacitor between HB and HS pins to be charged from VCC via the bootstrap diode. UCC256304 will remain in the CHARGE_BOOT state for a certain time to ensure the boot capacitor is fully charged. When LLC output voltage reaches a certain level, both PFC and LLC gets power from LLC transformer bias winding. When the load drops to below a certain level, LLC operates in burst mode

Fault conditions encountered by UCC256304 will cause operation to stop, or paused for a certain period of time followed by an automatic re-start. It is to ensure that while a persistent fault condition is present, it is not possible for UCC256304 or the power converter temperature to continue to rise as a result of the repeated re-start attempts.

Figure 49. Block Diagram of System States and Faults State Machine

Table 1 summarizes the inputs and outputs of Figure 49

The state machine is shown in Figure 50 and the description of the states and state transition conditions are in the tables below.

Figure 50. System States and Faults State Machine

Figure 51 only shows the most commonly used state transition (assuming no faults during start up states so all the states are captured in the timing diagram). Many different ways of state transitions may happen according to the state machine, but are not captured in this section.

In Figure 51, a normal start up procedure is shown. The system enters normal operation and then a fault (OCP, OVP, or OTP) happens.

The system is configured to be restart after 1s pause time.

Figure 51. Timing Diagram of System States and Faults

7.4.6 Waveform Generator State Machine

The waveform generator module consists of a state machine that implements hybrid hysteretic control, adaptive dead time, and ZCS protection. Each cycle of LLC operation is broken down into 4 separate periods: HSON, DTHL, LSON, and DTLH. In addition, there is an IDLE state and a WAKEUP state.

The initial state of this state machine is IDLE. In IDLE state, the system is operating in a low power mode. When WaveGenEn command is received, the state machine enters WAKEUP state to turn on various circuit blocks. Once the WAKEUP timer is expired, the system enters LSON (low side on) state. LSON state is followed by DTLH (dead time high to low) state, which is the dead time state. After DTLH state, the high side turns on and system enters HSON. HSON state is followed by DTHL (dead time low to high) state. After DTHL, the system goes back to LSON state again.

There are minimum and maximum timers in each of the states. The state transition conditions and descriptions are discussed in detail below.

Figure 52. Waveform Generator State Machine Block Diagram

Table 4 summarizes the inputs and outputs of the Waveform Generator State Machine Block Diagram

The state machine is shown in Figure 53 and the description of the states and state transition conditions are in Table 5.

Figure 53. Waveform Generator State Machine

8.2.1 Design Requirements

The design specifications are summarized in Table 8.

8.2.2 Detailed Design Procedure

8.2.2.3 LLC Gain Range

First, determine the transformer turns ratio by the nominal input and output voltages.

Equation 10.

Then determine the LLC gain range M_g(min) and M_g(max). Assume there is a 0.5-V drop in the rectifier diodes (V_f) and a further 0.5-V drop due to other losses (V_loss).

Equation 11.

Equation 12.

8.2.2.4 Select L_n and Q_e

L_n is the ratio between the magnetizing inductance and the resonant inductance.

Equation 13.

Q_e is the quality factor of the resonant tank.

Equation 14.

In this equation, R_e is the equivalent load resistance.

Selecting L_n and Q_e values should result in an LLC gain curve, as shown below, that intersects with M_g(min) and M_g(max) traces. The peak gain of the resulting curve should be larger than M_g(max). Details of how to select L_n and Q_e are not discussed here. They are available in the Application Note, UCC25630x Practical Design Guidelines and UCC256304 Design Calculator.

In this case, the selected L_n and Q_e values are:

Equation 15.

Equation 16.

8.2.2.5 Determine Equivalent Load Resistance

Determine the equivalent load resistance by Equation 17.

Equation 17.

8.2.2.6 Determine Component Parameters for LLC Resonant Circuit

Before determining the resonant tank component parameters, a nominal switching frequency (resonant frequency) should be selected. In this design, 100 kHz is selected as the resonant frequency.

Equation 18.

The resonant tank parameters can be calculated as the following:

Equation 19.

Equation 20.

Equation 21.

After the preliminary parameters are selected, find the closest actual component value that is available, re-check the gain curve with the selected parameters, and then run time domain simulation to verify the circuit operation.

The following resonant tank parameters are:

Equation 22.

Equation 23.

Equation 24.

Based on the final resonant tank parameters, the resonant frequency can be calculated:

Equation 25.

Based on the new LLC gain curve, the normalized switching frequency at maximum and minimum gain are given by:

Equation 26.

Equation 27.

The maximum and minimum switching frequencies are:

Equation 28.

Equation 29.

8.2.2.7 LLC Primary-Side Currents

The primary-side currents are calculated for component selection purpose. The currents are calculated based on a 110% overload condition.

The primary side RMS load current is given by:

Equation 30.

The RMS magnetizing current at minimum switching frequency is given by:

Equation 31.

The total current in resonant tank is given by:

Equation 32.

8.2.2.8 LLC Secondary-Side Currents

The total secondary side RMS load current is the current referred from the primary side current (I_oe) to the secondary side.

Equation 33.

In this design, the transformer’s secondary side has a center-tapped configuration. The current of each secondary transformer winding is calculated by:

Equation 34.

The corresponding half-wave average current is:

Equation 35.

8.2.2.10 LLC Resonant Inductor

The AC voltage across the resonant inductor is given by its impedance times the current:

Equation 36.

The inductor can be built or purchased according to the following specifications:

• Inductance: L_r = 61.5 µH
• Rated current: I_r = 1.009 A
• Terminal AC voltage:
• Frequency range: 50.3 kHz to 111.3 kHz

The minimum operating frequency during normal operation is that calculated above but during shutdown the LLC can operate at right above ZCS boundary condition, which is a lower frequency. The magnetic components in the resonant circuit, the transformer and resonant inductor, should be rated to operate at this lower frequency.

8.2.2.11 LLC Resonant Capacitor

This capacitor carries the full-primary current at a high frequency. A low dissipation factor part is needed to prevent overheating in the part.

The AC voltage across the resonant capacitor is given by its impedance times the current.

Equation 37.

Equation 38.

Peak voltage:

Equation 39.

Valley voltage:

Equation 40.

Rated current:

Equation 41.

8.2.2.12 LLC Primary-Side MOSFETs

Each MOSFET sees the input voltage as its maximum applied voltage. Choose the MOSFET voltage rating to be 1.5 times of the maximum bulk voltage:

Equation 42.

Choose the MOSFET current rating to be 1.1 times of the maximum primary side RMS current:

Equation 43.

8.2.2.13 Design Considerations for Adaptive Dead-Time

After the resonant tank is designed and the primary side MOSFET is selected, the ZVS operation of the converter needs to be double checked. ZVS can only be achieved when there is enough current left in the resonant inductor at the gate turn off edge to discharge the switch node. UCC256304 implements adaptive dead-time based on the slewing of the switch node. The slew detection circuit has a detection range of 1V/ns to 50 V/ns.

To check the ZVS operation, a series of time domain simulations are conducted, and the resonant current at the gate turn off edges are captured. An example plot is shown below:

Figure 54. Adaptive Dead-Time

The figure above assumes the maximum switching frequency occurs at 5% load, and system starts to burst at 5% load.

From this plot, the minimum resonant current left in the tank is I_min = 0.8 A in the interested operation range. In order to calculate the slew rate, the primary side switch node parasitic capacitance must be known. This value can be estimated from the MOSFET datasheet. In this case, C_switchnode = 400 pF. The minimum slew rate is given by:

Equation 44.

This is larger than 1 V/ns minimum detectable slew rate.

8.2.2.14 LLC Rectifier Diodes

The voltage rating of the output diodes is given by:

Equation 45.

The current rating of the output diodes is given by:

Equation 46.

8.2.2.15 LLC Output Capacitors

The LLC converter topology does not require an output filter although a small second stage filter inductor may be useful in reducing peak-to-peak output noise. Assuming that the output capacitors carry the rectifier’s full wave output current then the capacitor ripple current rating is:

Equation 47.

Use 20 V rating for 12-V output voltage:

Equation 48.

The capacitor’s RMS current rating is:

Equation 49.

Solid Aluminum capacitors with conductive polymer technology have high ripple-current ratings and are a good choice here. The ripple-current rating for a single capacitor may not be sufficient so multiple capacitors are often connected in parallel.

The ripple voltage at the output of the LLC stage is a function of the amount of AC current that flows in the capacitors. To estimate this voltage, assume that all the current, including the DC current in the load, flows in the filter capacitors.

Equation 50.

The capacitor specifications are:

• Voltage Rating: 20 V
• Ripple Current Rating: 4.84 A
• ESR: < 19 mΩ

8.2.2.17 BLK Pin Voltage Divider

BLK pin senses the LLC input voltage and determines when to turn on and off the LLC converter. Different versions of UCC256304 have different BLK thresholds.

Choose bulk startup voltage at 340 V, then the BLK resistor divider ratio can be calculated as below:

Equation 51.

The desired power consumption of the BLK pin resistor divider is P_BLKsns = 10 mW. The BLK sense resistor total value is given by:

Equation 52.

The lower BLK divider resistor value is given by:

Equation 53.

The higher BLK divider resistor value is given by:

Equation 54.

The actual bulk voltage thresholds can be calculated:

Equation 55.

Equation 56.

Equation 57.

Equation 58.

8.2.2.18 BW Pin Voltage Divider

BW pin senses the output voltage through the bias winding and protects the power stage from over voltage. The nominal output voltage is 12 V. The bias winding has 3 turns, and the secondary side winding has 2 turns. So the nominal voltage of the bias winding is given by:

Equation 59.

The desired OVP threshold in this design is 115% of the nominal value. The OVP threshold level in UCC256304 device is 4 V, so the nominal BW pin voltage is given by:

Equation 60.

Choose the lower resistor of the BW resistor divider to be 10 kΩ.

Equation 61.

The upper resistor can be calculated by:

Equation 62.

8.2.2.19 ISNS Pin Differentiator

ISNS pin sets the over current protection level. OCP1 is peak current protection level; OCP2 and OCP3 are average current protection levels. The threshold voltages are 0.6 V, 0.8 V, and 4 V, respectively.

Set OCP3 level at 150% of full load. Thus, the sensed average input current level at full load is given by:

Equation 63.

The current sense ratio can then be calculated:

Equation 64.

Select a current sense capacitor first, since there are less high voltage capacitor choices than resistors:

Equation 65.

Then calculate the required ISNS resistor value:

Equation 66.

After the current sense ratio is determined, the peak ISNS pin voltage at full load can be calculated:

Equation 67.

The peak resonant current at OCP1 level is given by:

Equation 68.

The peak secondary-side current at OCP1 level is given by:

Equation 69.

8.2.2.20 VCR Pin Capacitor Divider

The capacitor divider on the VCR pin sets two parameters: (1) the divider ratio of the resonant capacitor voltage; (2) the amount of frequency compensation to be added. The first criteria the capacitor divider needs to meet is that under over load condition, the peak-to-peak voltage on VCR pin is with in 6 V.

As derived earlier, the following relationship between VCOMP voltage, ΔVCR, switching period, input average current, and the VCR capacitor divider is shown in Equation 70

Equation 70.

In this equation, C₁ is the upper capacitor on the capacitor divider; C₂ is the lower capacitor on the capacitor divider. VCOMP is contributed by two parts – the divided resonant capacitor voltage, and the voltage generated by the VCR pin internal current sources. Define the contribution of the internal current source to be K_VCRRamp.

Equation 71.

Select C₁ and C₂ so that K_VCRRamp is within 0.1 ~ 0.6 range, and at over load condition, VCOMP is less than 6 V. In this example C₁ = 150 pF and C₂ = 15 nF is select.

8.2.2.21 Burst Mode Programming

The burst mode programming interface enables user to program a burst mode threshold voltage (VLL) which adaptively changes with input voltage. This way, consistent burst threshold can be achieved across V_IN range, thus making the efficiency curve more consistent across V_IN range.

The following relationship exists between VLL voltage and BLK pin voltage:

Equation 72.

In this equation, VLL is the burst mode threshold voltage; VBLK is BLK pin voltage; two parameters a and b can be programmed by two external resistors.

After soft start is done, the sensed BLK pin voltage is applied to LL/SS pin from inside the IC through a buffer. As shown in the figure below, this creates a difference between the current flowing through the programming resistor R_LLUpper and R_LLLower. The difference between the current flows into the LL/SS pin, mirrored and then applied to a 250-kΩ resistor R_LL. The voltage on R_LL is used as VLL.

Figure 55. Burst Mode Programming

The relationship between VLL and VBLK can then be derived:

Equation 73.

Equation 73 rearranged produces Equation 74

Equation 74.

To determine R_LLUpper and R_LLLower, two sets of (VLL, VBLK) values are required. VBLK can be measured directly from BLK pin. VLL level can be measured by inserting a 10-kΩ resistor between the feedback optocoupler emitter and ground. Assume the voltage measured on the 10-kΩ resistor is V_10k. Then VLL voltage can be calculated as:

Equation 75.

Remove the R_LLUpper. In this way, the VLL voltage is at its minimal value 0.7 V, which is determined by the internal circuit design. Then adjust the load current to the desired burst mode threshold load level, and make sure the power stage does not burst in this condition. For example, 10% load is the desired burst mode threshold level. With 10 A as the full-load condition, set the load current to 1 A. After the load current is set, change the input voltage to two different voltages and record two different readings (V10k, VBLK). Then based on Equation 74 and Equation 75, R_LLUpper and R_LLLower can be solved.

In this example select the lower resistor to be 402 kΩ and the upper resistor to be 732 kΩ.

8.2.2.22 Soft-Start Capacitor

The soft-start capacitor sets the speed of the soft-start ramp. The soft start time varies with load condition. At full load or over load condition, the soft start time is the longest. It is not easy to calculate the exact soft start time value. However, it can be estimated that under full load condition, the longest possible soft start time is given by:

Equation 76.

Using a 150-nF soft-start capacitor, gives the longest possible soft-start time as 42 ms according to Equation 76.

8.2.3 Application Curves

Figure 56.

Figure 58. Transient Response Load Step

Figure 60. Output Voltage Ripple

Figure 57.

Figure 59. Transient Response Load Release

Figure 61. X-Capacitor Discharge