AM263P4ACOLFZCZR ACTIVE

Processor Cores:

• Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400MHz
  • 16KB I-cache with 64-bit ECC per CPU core
  • 16KB D-cache with 32-bit ECC per CPU core
  • x256 integrated VIM per CPU Core
  • 256KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core cluster
  • Lockstep or Dual-core capable clusters
• Trigonometric Math Unit (TMU) for accelerating trigonometric functions
  • Up to 4x, one per R5F MCU core

Memory:

• 1x Flash Subsystem with OptiFlash memory technology and eXecute In Place (XIP) support
  • 1x Octal Serial Peripheral Interface (OSPI), up to 133MHz SDR and DDR
  • AM263P Flash-in-Package (ZCZ_F) variant includes 8MB OSPI Flash
• 3MB of On-Chip RAM (OCSRAM)
  • 6 Banks x 512KB
  • ECC error protection
  • Internal DMA engine support
  • Remote L2 Cache for external memory, software programmable up to 128KB per CPU core

System on Chip (SoC) Services and Architecture:

• 1x EDMA to support data movement functions
  • 2x Transfer Controllers (TPTC)
  • 1x Channel Controller (TPCC)
• Device Boot supported from the following interfaces:
  • UART (Primary/Backup)
  • QSPI NOR Flash (4S/1S) (Primary)
  • OSPI NOR Flash (8S 50MHz SDR Mode0, 8S 25MHz DDR XSPI) (Primary)
• Interprocessor communication modules
  • SPINLOCK module for synchronizing processes running on multiple cores
  • MAILBOX functionality implemented through CTRLMMR registers
• Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers
• Timer Modules:
  • 4x Windowed Watchdog Timer (WWDT)
  • 8x Real Time Interrupt (RTI) timer

General Connectivity:

• 6x Universal Asynchronous RX-TX (UART)
• 8x Serial Peripheral Interface (SPI) controllers
• 5x Local Interconnect Network (LIN) ports
• 4x Inter-Integrated Circuit (I2C) ports
• 8x Modular Controller Area Network (MCAN) modules with CAN-FD support
• 4x Fast Serial Interface Transmitters (FSITX)
• 4x Fast Serial Interface Receivers (FSIRX)
• Up to 139 General-Purpose I/O (GPIO) pins

Sensing & Actuation:

• Real-time Control Subsystem (CONTROLSS)
• Flexible Input/Output Crossbars (XBAR)
• 5x 12-bit Analog-to-Digital Converters (ADC)
  • 6-input SAR ADC up to 4MSPS
    • 6x Single-ended channels OR
    • 3x Differential channels
  • Highly Configurable ADC Digital Logic
    • XBAR Start of Conversion Triggers (SOC)
    • User-defined Sample and Hold (S+H)
    • Flexible Post-Processing Blocks (PPB)
• 1x Resolver subsystem (ZCZ-S and ZCZ-F packages) with:
  • 2x Resolver to Digital Converter (RDC) OR
  • 2x 12-bit ADCs can also be used for general purpose
    • 4-input SAR ADC up to 3MSPS
      • 4x Single-ended channels OR
      • 2x Differential channels
• 10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)
• 10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)
• 1x 12-bit Digital-to-Analog Converter (DAC)
• 32x Pulse Width Modulation (EPWM) modules
  • Single or Dual PWM channels
  • Advanced PWM Configurations
  • Extended HRPWM time resolution
• 16x Enhanced Capture (ECAP) modules
• 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
• 2x 4-Ch Sigma-Delta Filter Modules (SDFM)
• Additional Signal-multiplex Crossbars (XBAR)

Industrial Connectivity:

• Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS)
  • Dual core Programmable Real-Time Unit Subsystem (PRU0 / PRU1)
    • Deterministic Hardware
    • Dynamic Firmware
  • 20-channel enhanced input (eGPI) per PRU
  • 20-channel enhanced output (eGPO) per PRU
  • Embedded Peripherals and Memory
    • 1x UART, 1x ECAP, 1x MDIO, 1x IEP
    • 1x 32KB Shared General Purpose RAM
    • 2x 8KB Shared Data RAM
    • 1x 16KB IRAM per PRU
    • ScratchPad (SPAD), MAC/CRC
  • Digital encoder and sigma-delta control loops
  • The PRU-ICSS enables advanced industrial protocols including:
    • EtherCAT, Ethernet/IP™,
    • PROFINET, IO-Link for order
  • Dedicated Interrupt Controller (INTC)
  • Dynamic CONTROLSS XBAR Integration

High-Speed Interfaces:

• Integrated 3-port Gigabit Ethernet switch (CPSW) supporting up to two external ports
  • MII (10/100), RMII (10/100), or RGMII (10/100/1000)
  • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
  • Clause 45 MDIO PHY management
  • 512x ALE engine-based Packet Classifiers
  • Priority flow control with up to 2KB packet size
  • Four CPU hardware interrupt pacing
  • IP/UDP/TCP checksum offload in hardware

Security:

• Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
  • Arm Cortex-M4F based dedicated security controller
  • Isolated and secured RAMs
  • Peripherals like Timers, WWDT, RTC, Interrupt Controller
  • Safety related peripherals like CRC, ESM, PBIST
• Secure boot support
  • Device Take Over Protection
  • Hardware-enforced root-of-trust (RoT)
    • Support for two sets of RoT keys
  • Authenticated boot support
    • Encrypted boot support
  • SW Anti-rollback protection
• Debug security
  • Secure device debug only after cryptographic authentication
  • Support for permanent debug/JTAG disable
• Device ID and Key Management
  • Unique ID (SoC ID)
  • Support for OTP Memory (FUSEROM)
• Extensive Firewall Support
  • System Memory Protection Units (MPU) present at various interfaces
• Cryptographic Acceleration
  • Cryptographic cores with DMA Support
  • AES - 128/192/256-bit key sizes
  • SHA2 - 256/384/512-bit support
  • Deterministic random bit generator (DRBG) with pseudo and true random number generator (TRNG)
  • Public Key Accelerator (PKA) to assist in RSA/Elliptic Curve Cryptography (ECC) processing

Functional Safety:

• Enables design of systems with functional safety requirements
  • Error Signaling Module (ESM) with designated SAFETY_ERRORn pin
  • ECC or parity on calculation-critical memories
  • 4x Dual Clock Comparators (DCC)
  • 3x Self-Test Controller (STC)
  • Programmable Built-In Self-Test (PBIST) and fault-injection for CPU and on-chip RAM
  • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
• Functional Safety-Compliant targeted [Industrial]
  • Developed for functional safety applications
  • Documentation to be made available to aid IEC 61508 functional safety system design
  • Systematic capability up to SIL-3 targeted
  • Hardware integrity up to SIL-3 targeted
  • Safety-related certification
    • IEC 61508 planned
• Functional Safety-Compliant targeted [Automotive]
  • Developed for functional safety applications
  • Documentation to be made available to aid ISO 26262 functional safety system design
  • Systematic capability up to ASIL-D targeted
  • Hardware integrity up to ASIL-D targeted
  • Safety-related certification
    • ISO 26262 planned

Data Storage

• 1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface

Optimal Power Management Solution

• Recommended TPS653860-Q1 Power Management ICs (PMIC)
  • Companion PMIC specially designed to meet device power supply requirements
  • Flexible mapping and factory programmed configurations to support different use cases

Technology / Package:

• AEC-Q100 qualified for automotive applications
• 45nm technology
• ZCZ Package
  • AM263x Compatible (ZCZ-C)
    • Pin-to-Pin compatible option with AM263x
  • AM263Px Resolver (ZCZ-S)
    • Adds new Resolver Subsystem functionality
  • AM263Px Resolver with Flash-in-Package (ZCZ-F)
    • Includes 1x internally connected Silicon in Package (SIP) 64Mb ISSI IS25LX064-LWLA3 OSPI Flash device; up to 133MHz SDR and DDR
  • 324-pin NFBGA
  • 15.0mm x 15.0mm
  • 0.8mm pitch