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CDC7005

ACTIVE

High performance, low phase noise, low skew clock synchronizer that synchronizes ref clock to VCXO

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Data sheet

CDC7005

ACTIVE
Data sheet Order now

Product details

Function Clock generator Number of outputs 5 Output frequency (max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Op-amp for active loop filter, Programmable delay Rating Catalog
Function Clock generator Number of outputs 5 Output frequency (max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Op-amp for active loop filter, Programmable delay Rating Catalog
BGA (ZVA) 64 64 mm² 8 x 8 VQFN (RGZ) 48 49 mm² 7 x 7
  • High Performance 1:5 PLL Clock Synchronizer
  • Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
  • Synchronizes Frequencies up to 800 MHz (VCXO_IN)
  • Supports Five Differential LVPECL Outputs
  • Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
  • All Outputs Are Synchronized
  • Integrated Low-Noise OPA for External Low-Pass Filter
  • Efficient Jitter Screening From Low PLL Loop Bandwidth
  • Low-Phase Noise Characteristic
  • Programmable Delay for Phase Adjustments
  • Predivider Loop BW Adjustment
  • SPI Controllable Division Setting
  • Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
  • 3.3-V Power Supply
  • Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C
  • High Performance 1:5 PLL Clock Synchronizer
  • Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
  • Synchronizes Frequencies up to 800 MHz (VCXO_IN)
  • Supports Five Differential LVPECL Outputs
  • Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
  • All Outputs Are Synchronized
  • Integrated Low-Noise OPA for External Low-Pass Filter
  • Efficient Jitter Screening From Low PLL Loop Bandwidth
  • Low-Phase Noise Characteristic
  • Programmable Delay for Phase Adjustments
  • Predivider Loop BW Adjustment
  • SPI Controllable Division Setting
  • Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
  • 3.3-V Power Supply
  • Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.

The CDC7005 is characterized for operation from –40°C to 85°C.

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.

The CDC7005 is characterized for operation from –40°C to 85°C.
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Technical documentation

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Type Title Date
* Data sheet 3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet (Rev. L) 04 Jun 2009
Application brief Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B) 15 Dec 2009
Application note Basics of the CDC7005 Hold Function 13 Apr 2006
EVM User's guide CDC7005 (BGA Package) EVM (Rev. E) 28 Mar 2006
User guide CDC7005 (QFN Package) Evaluation Module Manual (Rev. B) 28 Mar 2006
EVM User's guide CDC7005 (BGA Package) EVM (Rev. D) 29 Dec 2005
User guide CDC7005 (QFN Package) Evaluation Module Manual (Rev. A) 29 Dec 2005
User guide CDC7005 (QFN Package) Evaluation Module Manual 20 Jul 2005
Application note Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A) 19 Jul 2005
EVM User's guide CDC7005EVM User Guide (Rev. C) 17 Feb 2005
Application note Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies 17 Dec 2004
User guide TSW2000 Receive Clock JItter Cleaning EVM 28 Jun 2004
Application note Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev 25 Jun 2004
Product overview ADS5500 + CDC7005 Product Bulletin 23 Jun 2004
Product overview TSW2000: TLK1201A & CDC7005 23 Jun 2004
Application note General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A) 16 Dec 2003
Application note General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner 21 Mar 2003

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Support software

SCAC037 — CDC7005 SPI Software with Labview 8.0 Runtime Engine

Supported products & hardware

Supported products & hardware

Products
Clock generators
CDC7005 — High performance, low phase noise, low skew clock synchronizer that synchronizes ref clock to VCXO
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Simulation model

CDC7005 IBIS Model

SCAC033.ZIP (34 KB) - IBIS Model
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Bill of materials (BOM)

TSW1000 EVM Bill of Materials

SLWR028.ZIP (166 KB)
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Calculation tool

CDC-CDCM7005-CALC — CDC7005 and CDCM7005 PLL Loop Bandwidth Calculator

This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump (...)
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Gerber file

CDC7005 EVM QFN Gerber Files

SCAC066.ZIP (537 KB)
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Gerber file

TSW1000 EVM Gerber Files

SLWC050.ZIP (532 KB)
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Package Pins CAD symbols, footprints & 3D models
BGA (ZVA) 64 Ultra Librarian
VQFN (RGZ) 48 Ultra Librarian
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