DS3486

ACTIVE

Quad RS-422/RS-423 Line Receiver

Product details

Number of receivers 4 Number of transmitters 0 Duplex Half Supply voltage (nom) (V) 5 Signaling rate (max) (Mbps) 10 IEC 61000-4-2 contact (±V) None Fault protection (V) -25 to 25 Common-mode range (V) -25 to 25 Number of nodes 32 Features Extended common mode Isolated No Supply current (max) (µA) 85000 Rating Catalog Operating temperature range (°C) 0 to 70
Number of receivers 4 Number of transmitters 0 Duplex Half Supply voltage (nom) (V) 5 Signaling rate (max) (Mbps) 10 IEC 61000-4-2 contact (±V) None Fault protection (V) -25 to 25 Common-mode range (V) -25 to 25 Number of nodes 32 Features Extended common mode Isolated No Supply current (max) (µA) 85000 Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Four Independent Receivers
  • TRI-STATE Outputs
  • Internal Hysteresis −140 mV (typ)
  • Fast Propagation Times −19 ns (typ)
  • TTL Compatible Outputs
  • 5V Supply
  • Pin Compatible and Interchangeable with MC3486

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  • Four Independent Receivers
  • TRI-STATE Outputs
  • Internal Hysteresis −140 mV (typ)
  • Fast Propagation Times −19 ns (typ)
  • TTL Compatible Outputs
  • 5V Supply
  • Pin Compatible and Interchangeable with MC3486

All trademarks are the property of their respective owners.

Texas Instruments' quad RS-422, RS-423 receiver features four independent receivers which comply with EIA Standards for the electrical characteristics of balanced/unbalanced voltage digital interface circuits. Receiver outputs are 74LS compatible, TRI-STATE structures which are forced to a high impedance state when the appropriate output control pin reaches a logic zero condition. A PNP device buffers each output control pin to assure minimum loading for either logic one or logic zero inputs. In addition, each receiver has internal hysteresis circuitry to improve noise margin and discourage output instability for slowly changing input waveforms.

Texas Instruments' quad RS-422, RS-423 receiver features four independent receivers which comply with EIA Standards for the electrical characteristics of balanced/unbalanced voltage digital interface circuits. Receiver outputs are 74LS compatible, TRI-STATE structures which are forced to a high impedance state when the appropriate output control pin reaches a logic zero condition. A PNP device buffers each output control pin to assure minimum loading for either logic one or logic zero inputs. In addition, each receiver has internal hysteresis circuitry to improve noise margin and discourage output instability for slowly changing input waveforms.

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* Data sheet DS3486 Quad RS-422, RS-423 Line Receiver datasheet (Rev. D) 15 Apr 2013

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